Andrew Waterman
c49cb10c74
Merge pull request #42 from terpstra/ahb
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Ahb
2016-05-24 17:02:15 -07:00
Andrew Waterman
88cc91db75
Ignore way_en in MetadataArray for direct-mapped caches
2016-05-24 15:47:09 -07:00
Wesley W. Terpstra
a012341d96
ahb: TileLink => AHB bridge, including atomics and bursts
2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
ace9362d81
ahb: amoalu does not need so many parameters! (i want to reuse it)
2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
00d31dc5c5
bram: use new hasti definitions
2016-05-24 13:35:16 -07:00
Albert Ou
ee0acc1d07
Fix BRAM assertion condition
2016-05-23 13:19:53 -07:00
Colin Schmidt
3e0b5d6fd9
Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release,
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but would otherwise be allocated.
Closes #45
2016-05-20 16:35:30 -07:00
Ken McMillan
fd83d20857
Use a def instead of a lazy val in ManagerCoherenceAgent.
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Prevents C++ emulator from randomizing inputs in unit testing.
Closes #44
2016-05-20 16:31:12 -07:00
Ken McMillan
d69446e177
Add config classes to drive unit testing of L2 TileLink agents.
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Closes #43
2016-05-20 16:15:43 -07:00
Howard Mao
4f84d8f757
make sure to hook up finish in ClientTileLinkEnqueuer
2016-05-18 13:13:34 -07:00
Howard Mao
f138819992
fix order of assignments in ManagerTileLinkNetworkPort
2016-05-11 16:45:00 -07:00
Andrew Waterman
533b229175
Improve PLIC QoR
2016-05-10 17:03:56 -07:00
Andrew Waterman
e15e9c5085
First draft of interrupt controller
2016-05-10 00:25:13 -07:00
Howard Mao
14a6e470c9
transform ids in TL -> NASTI converter if necessary
2016-05-07 21:19:27 -07:00
Howard Mao
1ed6d6646d
move NastiROM and HastiRAM into rom.scala and bram.scala
2016-05-06 11:31:22 -07:00
Howard Mao
77e859760c
add a Hasti RAM alongside the Nasti ROM
2016-05-06 11:31:22 -07:00
Howard Mao
f26c422544
assert that TileLink router has valid route
2016-05-03 12:18:06 -07:00
Andrew Waterman
cc4102f8de
Add trivial version of PRCI block
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It doesn't really do anything besides deliver deliver IPIs yet.
2016-05-02 17:49:10 -07:00
Andrew Waterman
72731de25a
Take a stab at the PRCI-Rocket interface
2016-05-02 15:20:33 -07:00
Andrew Waterman
695c4c5096
Support both Get and GetBlock on ROMSlave
2016-04-30 17:34:12 -07:00
Albert Ou
6f052a740c
Add TileLink BRAM slave
2016-04-29 14:10:44 -07:00
Andrew Waterman
1df68a25fd
Address Map refactoring
2016-04-28 16:08:58 -07:00
Wei Song
ed5bdf3c23
print the base address of each SCR as indicated
2016-04-28 16:31:56 +01:00
Andrew Waterman
81ff127dc3
Clean up TileLinkRecursiveInterconnect a bit
2016-04-27 14:53:11 -07:00
Andrew Waterman
87cecc336f
Add new RTC as TileLink slave, not AXI master
2016-04-27 11:55:35 -07:00
Andrew Waterman
eb0b5ec61e
Remove stats CSR
2016-04-27 00:16:21 -07:00
Andrew Waterman
9044a4a4b7
Replace NastiROM with ROMSlave, which uses TileLink
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I'm not wedded to the name.
2016-04-27 00:15:30 -07:00
Andrew Waterman
356efe2fd5
Simplify TileLink Narrower
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It's not necessary to use addr_beat to determine where to put the Grant
data. Just stripe it across all lanes.
This also gets rid of a dependence on addr_beat in Grant. If we move
towards a regime where TileLink is only narrowed, not widened, we may
be able to drop the field altogether.
2016-04-26 16:44:54 -07:00
Wei Song
f6e44b1348
avoid logical to physical header conversion overflow
2016-04-22 17:47:34 +01:00
Howard Mao
f9de99ed40
changes to match junctions no-mmio-base
2016-04-21 15:35:37 -07:00
Howard Mao
9b3faff5a5
add id field to write data channel in TL -> AXI converter
2016-04-19 09:46:31 -07:00
Howard Mao
152645b1bc
use manager_id instead of client_id in GrantFromSrc and FinishToDst
2016-04-07 11:20:16 -07:00
Howard Mao
f88b6932ce
don't add pending reads if data is already available
2016-04-06 15:43:21 -07:00
Howard Mao
31e145eaf0
fix BroadcastHub allocation and routing
2016-04-05 16:21:18 -07:00
Howard Mao
f68a7dabdf
fix AXI -> TL converter
2016-04-04 19:42:25 -07:00
Howard Mao
f956d4edfb
NASTI does not right-justify data; fix in converter
2016-04-01 20:55:00 -07:00
Henry Cook
c292a07ace
Bugfix for merged voluntary releases in L2Cache.
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Track pending release beats for voluntary releases that are merged by Acquire Trackers.
Closes #23 and #24 .
2016-04-01 19:57:47 -07:00
Henry Cook
82bdf3afcb
Fix LRSC starvation bug by punching Finish messages out to caching clients via a new TileLinkNetworkPort.
2016-04-01 16:17:27 -07:00
Andrew Waterman
8957b5e973
Improve simulation speed of BasicCrossbar
2016-04-01 13:28:11 -07:00
Howard Mao
3083bbca21
fix TileLink arbiters and add memory interconnect and memory selector
2016-03-31 18:15:51 -07:00
Howard Mao
cf363b1fe4
add TileLink interconnect generator
2016-03-31 14:12:55 -07:00
Howard Mao
d78066db5c
chisel3 fix for split metadata
2016-03-30 22:11:19 -07:00
Howard Mao
3d990bdbef
workaround for Chisel3 name-aliasing issue
2016-03-30 19:15:22 -07:00
Howard Mao
8e7f18084b
switch RTC to use TileLink instead of AXI
2016-03-28 12:23:16 -07:00
Howard Mao
7f8f138d6a
fix addPendingBitWhenPartialWritemask
2016-03-24 20:01:50 -07:00
Howard Mao
11bd15432a
fix bug in RTC
2016-03-24 20:01:50 -07:00
Howard Mao
00b3908d92
git rid of reorder queue in narrower
2016-03-24 20:01:50 -07:00
Palmer Dabbelt
c6e974b110
Merge pull request #30 from ucb-bar/chisel3
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Chisel 3 support
2016-03-24 11:52:02 -07:00
Palmer Dabbelt
c9e1b72972
Don't assign SInt(-1) to a UInt
2016-03-23 16:24:27 -07:00
Palmer Dabbelt
aa22f175c3
Add cloneType methods for Chisel3
2016-03-21 13:35:02 -07:00
