354cb2d5ec
Don't stall I$ response when resolving a branch misprediction
...
This avoids a fetch bubble.
Not clear if this is the best way to do it. Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
2016-05-24 15:05:41 -07:00
d7790ac6a4
WIP on blocking D$
2016-05-24 15:05:41 -07:00
335e2c8a1e
Support disabling atomics extension
2016-05-24 15:05:41 -07:00
765b90f6a4
Stall on D$ lockups less conservatively
2016-05-24 15:05:41 -07:00
a3061047e3
Instantiate blocking D$ when NMSHRS=0
2016-05-24 15:05:41 -07:00
80482890fd
Don't rely on tag value for nacks
2016-05-24 15:05:41 -07:00
e19c5e5d2c
IOMSHR: support atomic operations
2016-05-24 15:00:50 -07:00
a012341d96
ahb: TileLink => AHB bridge, including atomics and bursts
2016-05-24 14:58:27 -07:00
ace9362d81
ahb: amoalu does not need so many parameters! (i want to reuse it)
2016-05-24 14:58:27 -07:00
b921bae107
ahb: eliminate trait abused for constants
2016-05-24 14:20:45 -07:00
200c69c106
ahb: support hmastlock acquistion of crossbar
2016-05-24 14:20:45 -07:00
e1e8eda419
ahb: add a test SRAM
2016-05-24 14:20:42 -07:00
1db40687c6
ahb: eliminate now-unnecesary non-standard hreadyin
2016-05-24 14:14:22 -07:00
15cad8414d
ahb: put signals in the order they appear in signal traces in the spec
2016-05-24 14:14:22 -07:00
f30f8d9f79
ahb: reduce obsolete degenerate cases of a crossbar
2016-05-24 14:14:22 -07:00
0368b6db6b
ahb: replace defective crossbar with a functional one
...
The previous crossbar had the following bugs:
1. a bursting master could be preempted
the AHB-lite spec requires a slave receive the entire burst
2. a waited master could be replaced
the AHB-lite spec requires haddr/etc to remain unchanged
3. hmastlock did no ensure exclusive access
atomic operations could be pre-empted
2016-05-24 14:14:22 -07:00
2b37f37335
ahb: helper methods
2016-05-24 14:14:21 -07:00
ef2aae26a8
ahb: rename hreadyout to standard hready, mark hreadyin for death
2016-05-24 14:14:21 -07:00
2f8a77f27a
ahb: include all AHB-lite constants
2016-05-24 14:14:21 -07:00
7896c4157e
ahb: parameterize poci
2016-05-24 14:14:21 -07:00
93447eb274
ahb: make hasti parameters location sensitive
2016-05-24 14:14:17 -07:00
00d31dc5c5
bram: use new hasti definitions
2016-05-24 13:35:16 -07:00
ee0acc1d07
Fix BRAM assertion condition
2016-05-23 13:19:53 -07:00
05c0808ff2
Update trace generation and checking scripts
...
Pass the elf file (that specifies the tohost and fromhost addresses)
to the emulator in the trace generator & checker scripts.
2016-05-23 17:02:15 +01:00
7bc38383de
add (non-working) blocking data cache
2016-05-20 18:59:05 -07:00
3e0b5d6fd9
Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release,
...
but would otherwise be allocated.
Closes #45
2016-05-20 16:35:30 -07:00
fd83d20857
Use a def instead of a lazy val in ManagerCoherenceAgent.
...
Prevents C++ emulator from randomizing inputs in unit testing.
Closes #44
2016-05-20 16:31:12 -07:00
f228309bd1
add assertion to make sure SimpleHellaCacheIF doesn't get exception
2016-05-20 16:30:27 -07:00
d69446e177
Add config classes to drive unit testing of L2 TileLink agents.
...
Closes #43
2016-05-20 16:15:43 -07:00
87be2bcd60
make sure TraceGen addresses are correct
2016-05-20 16:12:11 -07:00
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
4f84d8f757
make sure to hook up finish in ClientTileLinkEnqueuer
2016-05-18 13:13:34 -07:00
abb0e2921b
return non-zero exit codes when an assertion fires
...
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
2016-05-18 12:57:58 -07:00
b396c68577
bump torture for priv-1.9 test-env
2016-05-17 22:02:38 -07:00
b0ae003981
add firrtl to regression makefile
...
this makes it easier to test chisel3 builds
e.g. the local buildbot can now test a bunch of configs
2016-05-17 17:34:20 -07:00
4aef567a80
Fix MMIO bug: replay_next wasn't set
2016-05-13 17:59:53 -07:00
742c05d6a7
Pipeline D$->I$ control paths
...
These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
2016-05-13 17:07:28 -07:00
684d902059
Fix PLIC instantiation when S-mode is disabled
2016-05-13 11:22:46 -07:00
f138819992
fix order of assignments in ManagerTileLinkNetworkPort
2016-05-11 16:45:00 -07:00
6aa708bcee
Disable MMIO by default to avoid disconnected nets
2016-05-11 13:12:39 -07:00
3fe00ce32a
Update README.md
...
- Removed instruction to checkout riscv-tests (as they are now globally installed when building the riscv-tools).
- Clarified the riscv-tools set-up information to clarify that the rocket-chip/riscv-tools is the version to build.
2016-05-10 22:12:02 -07:00
533b229175
Improve PLIC QoR
2016-05-10 17:03:56 -07:00
fbff46d27d
bump rocket
2016-05-10 10:57:03 -07:00
aac89ca1f0
Add PLIC
2016-05-10 00:27:31 -07:00
e15e9c5085
First draft of interrupt controller
2016-05-10 00:25:13 -07:00
df479d7935
don't make MIFTagBits a computed parameter
2016-05-08 11:04:58 -07:00
14a6e470c9
transform ids in TL -> NASTI converter if necessary
2016-05-07 21:19:27 -07:00
3b0e9167fa
add AXI to AHB converter and more conformant HASTI RAM
2016-05-06 11:32:03 -07:00
3e759d2575
add Hasti test to unit test
2016-05-06 11:31:43 -07:00
1ed6d6646d
move NastiROM and HastiRAM into rom.scala and bram.scala
2016-05-06 11:31:22 -07:00
