4045a07eda
Remove need for separate riscv-tests for groundtest
2016-05-03 18:29:46 -07:00
8f891437b5
fix CacheFillTest
2016-05-03 14:57:05 -07:00
15f4af19cf
Remove HTIF CPU port
2016-05-03 13:55:59 -07:00
9dd23a603a
Remove HTIF port
2016-05-03 13:41:58 -07:00
6cb0979ac4
fix CacheFillTest
2016-05-03 13:35:38 -07:00
487d0b356e
fixes to get groundtest working with priv-1.9 changes
2016-05-03 13:09:44 -07:00
518d510622
only write out finish from tile 0 in groundtest
2016-05-03 13:09:22 -07:00
f26c422544
assert that TileLink router has valid route
2016-05-03 12:18:06 -07:00
b95f095aca
write to multiple possible tohost locations
2016-05-02 20:11:20 -07:00
5352497edb
MPRV takes effect regardless of privilege mode
2016-05-02 19:53:25 -07:00
4b4e8f7f62
fixes for priv-1.9 changes
2016-05-02 18:25:02 -07:00
5cbcc41515
get rid of unused imports
2016-05-02 18:23:46 -07:00
be21f6962b
make GlobalAddrHashMap a config variable
2016-05-02 18:22:43 -07:00
c7c8ae5468
Instantiate PRCI block
2016-05-02 18:08:33 -07:00
f784f4da93
Rename PRCICoreIO to PRCITileIO
2016-05-02 18:08:01 -07:00
cc4102f8de
Add trivial version of PRCI block
...
It doesn't really do anything besides deliver deliver IPIs yet.
2016-05-02 17:49:10 -07:00
6d1e82bddf
Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port
2016-05-02 15:21:55 -07:00
72731de25a
Take a stab at the PRCI-Rocket interface
2016-05-02 15:20:33 -07:00
000e20f937
Remove MIPI; make mip.MSIP read-only
...
The PRCI block outside the core will provide IPIs eventually
2016-05-02 15:18:41 -07:00
83fa489cef
Stop using HTIF CSR port
...
The port itself is still present to keep other stuff compiling.
2016-05-02 14:40:52 -07:00
c4d2d29e80
Stub out debug module, rather than leaving it floating
2016-04-30 22:37:39 -07:00
0ff4fd0ccd
Fix IOMSHR to send finishes for stores
2016-04-30 22:20:29 -07:00
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
695c4c5096
Support both Get and GetBlock on ROMSlave
2016-04-30 17:34:12 -07:00
491184a8f8
ERET -> xRET; remove mcfgaddr
2016-04-30 17:32:51 -07:00
5af98145b9
don't signal bad physical address on TLB miss
2016-04-30 17:31:46 -07:00
6f052a740c
Add TileLink BRAM slave
2016-04-29 14:10:44 -07:00
d0aa4c722d
More WIP on new memory map
2016-04-28 16:15:31 -07:00
cae4265f3b
Change mcfgaddr pointer
2016-04-28 16:14:05 -07:00
e4ace55d77
Address Map refactoring
2016-04-28 16:12:35 -07:00
1df68a25fd
Address Map refactoring
2016-04-28 16:08:58 -07:00
ed5bdf3c23
print the base address of each SCR as indicated
2016-04-28 16:31:56 +01:00
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
739cf07637
Remove mtime/mtimecmp
...
The RTC is now a device that lives on the MMIO bus.
2016-04-27 14:54:51 -07:00
81ff127dc3
Clean up TileLinkRecursiveInterconnect a bit
2016-04-27 14:53:11 -07:00
c8b1f0801b
Remove start address option from AddrMapEntries
...
It appears to never be used, and clutters things. The new invariant is
that AddrMaps are relative and AddrHashMaps are absolute.
2016-04-27 14:52:05 -07:00
d3dee2c6c6
support countSlaves on empty address maps
2016-04-27 14:51:52 -07:00
87cecc336f
Add new RTC as TileLink slave, not AXI master
2016-04-27 11:55:35 -07:00
fb5c38c186
Handle invalidate_lr in cache arbiter, not tile
2016-04-27 11:22:04 -07:00
b99db83e67
Avoid needless Vec generation
2016-04-27 00:28:39 -07:00
8acec8eb36
Remove dead code from BTB
2016-04-27 00:28:12 -07:00
eb0b5ec61e
Remove stats CSR
2016-04-27 00:16:21 -07:00
9044a4a4b7
Replace NastiROM with ROMSlave, which uses TileLink
...
I'm not wedded to the name.
2016-04-27 00:15:30 -07:00
356efe2fd5
Simplify TileLink Narrower
...
It's not necessary to use addr_beat to determine where to put the Grant
data. Just stripe it across all lanes.
This also gets rid of a dependence on addr_beat in Grant. If we move
towards a regime where TileLink is only narrowed, not widened, we may
be able to drop the field altogether.
2016-04-26 16:44:54 -07:00
fe8c91f620
Fix IOMSHR state machine bug
...
Sending the finish too early causes the CPU response to get dropped.
attn @zhemao
2016-04-26 15:32:25 -07:00
5fd5b58743
Remove stats CSR
2016-04-26 15:31:32 -07:00
d93677a343
Support larger cache sets when not using VM
2016-04-26 15:31:32 -07:00
5dbf9640e2
Use TLB flush signal to I$ explicitly
2016-04-22 15:41:31 -07:00
84fd45fd77
Pass TLB flush signal to I$ explicitly
2016-04-22 15:20:17 -07:00
48170fd9aa
add default cases to configs that use CDEMatchError
...
this avoids filling in the stack trace every time
a config doesn't contain the parameter
2016-04-22 12:14:58 -07:00
Howard Mao
Andrew Waterman
Albert Ou
Wei Song
Yunsup Lee
Colin Schmidt