It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip. We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
(1) Introduce tracegen.py, a script that invokes the emulator (built
with TraceGenConfig), sending a SIGTERM once all cores are finished.
(2) Update toaxe.py to gather some statistics about the trace.
(3) Introduce tracestats.py, which displays the stats in a useful way.
(4) Introduce tracegen+check.py, a top-level script that generates
traces, checks them, and emits stats. If this commit is pulled, it
should be done after pulling my latest groundtest commit.
To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).
Closes#18Closes#20
