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riscv
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rocket-chip
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8c7e29eacd5a05dec569decf2a614e4f3bd458b2
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Palmer Dabbelt
8c7e29eacd
Avoid generating 0-width UInts
...
Chisel3 requires a 1-bit width to represent UInt(0).
2016-03-10 17:37:40 -08:00
uncore
Avoid generating 0-width UInts
2016-03-10 17:37:40 -08:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%