Howard Mao
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7b7e954133
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make sure DummyPTW does not invalidate the TLB
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2016-03-22 19:59:58 -07:00 |
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Matthew Naylor
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bda5772e98
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Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too.
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2016-03-18 12:11:11 +00:00 |
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Matthew Naylor
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04be438847
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Avoid conflicting assigments to registers in timers. Give priority to start over stop.
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2016-03-16 12:54:19 -07:00 |
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Andrew Waterman
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137b77d780
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Merge pull request #4 from ucb-bar/chisel3
Work around Chisel3's lack of 0-width wires
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2016-03-15 17:30:34 -07:00 |
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Palmer Dabbelt
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50f61687de
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Work around Chisel3's lack of 0-width wires
This is super ugly, but it's necessary to get Chisel3 to compile. Note
that this still fails simulations in Chisel3, so it might be wrong.
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2016-03-14 22:50:37 -07:00 |
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Andrew Waterman
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13dcb96b7f
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Update TLB interface
n.b. no need to set mprv, since prv = S.
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2016-03-14 17:55:19 -07:00 |
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Andrew Waterman
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3e721fe80b
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Merge pull request #2 from ucb-bar/chisel3
Pass a BitPat to Lookup
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2016-03-06 04:27:52 -08:00 |
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Palmer Dabbelt
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bf06ba0d37
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Pass a BitPat to Lookup
This is the only supported type of Lookup in Chisel 3.
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2016-03-05 18:50:56 -08:00 |
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Howard Mao
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c2e9971b5f
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move toaxe.py script into top-level Rocket-Chip repo
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2016-02-23 08:52:32 -08:00 |
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Matthew Naylor
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1b6871f3d8
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Add author, affiliation, and sponsor info to trace-generator files.
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2016-02-23 15:30:11 +00:00 |
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Howard Mao
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91e3c9b96f
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reuse generator parameters for tracegen
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2016-02-22 09:53:31 -08:00 |
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Matthew Naylor
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e63fc3bb44
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Added trace generator
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2016-02-22 08:43:34 -08:00 |
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Howard Mao
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da302504a5
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get rid of sequential same id get regression in broadcast regression suite
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2016-02-19 23:14:34 -08:00 |
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Howard Mao
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000af5e662
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add NastiIOHostIO converter test
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2016-02-19 11:21:53 -08:00 |
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Howard Mao
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f290157cb3
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check that MultiWidthFifo count is correct
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2016-02-17 13:36:07 -08:00 |
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Howard Mao
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4915a258f6
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add unit test for some modules
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2016-02-16 23:10:55 -08:00 |
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Howard Mao
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e90dfcb403
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add test for NASTI to TL converter
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2016-02-10 11:07:37 -08:00 |
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Howard Mao
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428fa14601
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fix DummyPTW response
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2016-01-27 15:33:02 -08:00 |
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Howard Mao
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a59ff38b67
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use MMIO for DMA requests instead of separate channel
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2016-01-27 15:33:02 -08:00 |
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Howard Mao
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04e1f8c5c3
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lowercase SMI to Smi
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2016-01-11 16:18:49 -08:00 |
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Howard Mao
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80d97d5f9e
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test DMA streaming
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2016-01-06 21:38:12 -08:00 |
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Howard Mao
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b8d0376d3f
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Merge pull request #1 from ucb-bar/dma
add DMA test
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2015-12-22 10:33:48 -05:00 |
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Howard Mao
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24eecee148
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add DMA test
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2015-12-16 21:26:22 -08:00 |
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Howard Mao
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4858ca9a60
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add a regression to test proper writeback
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2015-12-16 21:05:56 -08:00 |
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Howard Mao
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176d3c890c
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add some more regression tests
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2015-12-15 23:00:17 -08:00 |
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Howard Mao
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484e8ce20b
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add regression tests for catching specific memory bugs
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2015-12-06 02:57:45 -08:00 |
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Howard Mao
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158d1d870c
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do all the writes before doing the gets in GeneratorTest
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2015-11-21 09:42:00 -08:00 |
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Howard Mao
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49c6b1ad1c
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add CacheFillTest
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2015-11-19 00:15:36 -08:00 |
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Howard Mao
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640544ea5a
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generalize test harness
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2015-11-18 22:54:05 -08:00 |
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Howard Mao
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f325874420
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make sure timeout doesn't trigger spuriously on reset
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2015-11-18 22:53:50 -08:00 |
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Howard Mao
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8bc90ab9bd
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separate out common functionality
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2015-11-18 20:53:19 -08:00 |
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Howard Mao
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10f4c6c71c
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interleave cached and uncached requests
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2015-11-12 11:34:44 -08:00 |
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Howard Mao
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7cae6cedf5
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finished bit should be set true if generator not being used
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2015-11-11 18:51:16 -08:00 |
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Howard Mao
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f93872d6b4
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make sure cached generator actually drives finished signal
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2015-11-11 18:45:36 -08:00 |
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Howard Mao
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eeda3dd770
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add README
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2015-11-11 18:30:19 -08:00 |
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Howard Mao
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9482d944ca
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make Uncached generator vary the alloc bit
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2015-11-11 18:26:56 -08:00 |
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Howard Mao
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8a6b231b08
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explicitly configure the number of requests being sent by generators
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2015-11-11 14:32:19 -08:00 |
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Howard Mao
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13f62e0364
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make sure generators can detect lockup
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2015-11-10 14:39:56 -08:00 |
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Howard Mao
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520925c207
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fix up build.sbt and add gitignore
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2015-11-10 13:38:39 -08:00 |
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Howard Mao
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d844bee310
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properly shift grant data when checking correctness
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2015-10-31 18:58:05 -07:00 |
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Howard Mao
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644b66a3a8
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selectively enable or disable uncached and cached generators
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2015-10-31 17:43:25 -07:00 |
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Howard Mao
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bcc631f756
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generate word-size requests in uncached generator
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2015-10-31 17:43:08 -07:00 |
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Howard Mao
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c1f42ce3d4
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add an L1 cache request generator
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2015-10-30 12:49:57 -07:00 |
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Howard Mao
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3103fa8da2
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rename tl to mem in generator
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2015-10-27 17:14:56 -07:00 |
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Howard Mao
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aeb9c86459
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use the uncached port instead of the cached port
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2015-10-26 23:09:36 -07:00 |
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Howard Mao
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b22088d934
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make sure data checked is same as data sent
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2015-10-26 21:55:04 -07:00 |
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Howard Mao
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2b252bc6ff
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first commit
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2015-10-26 21:43:50 -07:00 |
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