add NastiIOHostIO converter test
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@ -2,6 +2,8 @@ package groundtest
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import uncore._
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import cde.Parameters
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abstract class UnitTest extends Module {
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@ -11,6 +13,113 @@ abstract class UnitTest extends Module {
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}
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}
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class NastiToHostTestDriver(htifW: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val start = Bool(INPUT)
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val nasti = new NastiIO
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val reset = Bool(INPUT)
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}
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val DCOUNT_ADDR = 0x00
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val RFIFO_ADDR = 0x04
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val WFIFO_ADDR = 0x00
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val RESET_ADDR = 0x7c
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val (s_idle :: s_fifo_wr_addr :: s_fifo_wr_data :: s_fifo_wr_resp ::
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s_rst_wr_addr :: s_rst_wr_data :: s_rst_wr_resp ::
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s_cnt_rd_addr :: s_cnt_rd_data :: s_fifo_rd_addr :: s_fifo_rd_data ::
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s_done :: Nil) = Enum(Bits(), 12)
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val state = Reg(init = s_idle)
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val nBeats = 4
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val (wr_cnt, wr_done) = Counter(
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state === s_fifo_wr_data && io.nasti.w.ready, nBeats)
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val (rd_cnt, rd_done) = Counter(
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state === s_fifo_rd_data && io.nasti.r.valid, nBeats)
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val test_data = Vec.tabulate(nBeats) { i => UInt(i * 0x304, 32) }
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io.nasti.ar.valid := (state === s_cnt_rd_addr) || (state === s_fifo_rd_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = Mux(state === s_cnt_rd_addr, UInt(DCOUNT_ADDR), UInt(RFIFO_ADDR)),
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len = Mux(state === s_cnt_rd_addr, UInt(0), UInt(nBeats - 1)),
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size = UInt("b010"),
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burst = BURST_FIXED)
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io.nasti.aw.valid := (state === s_fifo_wr_addr) || (state === s_rst_wr_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = Mux(state === s_rst_wr_addr, UInt(RESET_ADDR), UInt(WFIFO_ADDR)),
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len = Mux(state === s_rst_wr_addr, UInt(0), UInt(nBeats - 1)),
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size = UInt("b010"),
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burst = BURST_FIXED)
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io.nasti.w.valid := (state === s_fifo_wr_data) || (state === s_rst_wr_data)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = Mux(state === s_rst_wr_data, UInt(0), test_data(wr_cnt)),
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last = Mux(state === s_rst_wr_data, Bool(true), (wr_cnt === UInt(nBeats - 1))))
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io.nasti.r.ready := (state === s_fifo_rd_data) || (state === s_cnt_rd_data)
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io.nasti.b.ready := (state === s_fifo_wr_resp) || (state === s_rst_wr_resp)
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when (state === s_idle && io.start) { state := s_fifo_wr_addr }
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when (io.nasti.ar.fire()) {
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state := Mux(state === s_fifo_rd_addr, s_fifo_rd_data, s_cnt_rd_data)
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}
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when (io.nasti.aw.fire()) {
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state := Mux(state === s_fifo_wr_addr, s_fifo_wr_data, s_rst_wr_data)
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}
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when (wr_done) { state := s_fifo_wr_resp }
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when (state === s_rst_wr_data && io.nasti.w.ready) {
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state := s_rst_wr_resp
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}
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when (io.nasti.b.fire()) {
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state := Mux(state === s_fifo_wr_resp, s_rst_wr_addr, s_cnt_rd_addr)
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}
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when (state === s_cnt_rd_data && io.nasti.r.valid) {
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state := s_fifo_rd_addr
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}
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when (rd_done) { state := s_done }
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io.finished := (state === s_done)
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assert(state =/= s_fifo_rd_data || !io.nasti.r.valid ||
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io.nasti.r.bits.data === test_data(rd_cnt),
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"NastiIO to HostIO result does not match")
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assert(state =/= s_cnt_rd_data || !io.nasti.r.valid ||
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io.nasti.r.bits.data === UInt(nBeats),
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"NastiIO to HostIO count is not correct")
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assert(state =/= s_rst_wr_data || !io.nasti.w.ready || io.reset,
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"NastiIO to HostIO reset did not fire")
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}
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class NastiIOHostIOConverterTest(implicit p: Parameters) extends UnitTest {
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val conv = Module(new NastiIOHostIOConverter(16)(p.alterPartial({
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case NastiKey => NastiParameters(
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dataBits = 32,
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addrBits = p(PAddrBits),
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idBits = 5)
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})))
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val driver = Module(new NastiToHostTestDriver(16))
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conv.io.nasti <> driver.io.nasti
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conv.io.host.out.bits := conv.io.host.in.bits
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conv.io.host.out.valid := conv.io.host.in.valid
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conv.io.host.in.ready := conv.io.host.out.ready
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driver.io.reset := conv.io.reset
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driver.io.start := io.start
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io.finished := driver.io.finished
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}
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class MultiWidthFifoTest extends UnitTest {
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val big2little = Module(new MultiWidthFifo(16, 8, 8))
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val little2big = Module(new MultiWidthFifo(8, 16, 4))
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@ -92,7 +201,9 @@ class MultiWidthFifoTest extends UnitTest {
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class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
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disablePorts()
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val tests = Seq(Module(new MultiWidthFifoTest))
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val tests = Seq(
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Module(new MultiWidthFifoTest),
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Module(new NastiIOHostIOConverterTest))
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val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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