riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

lowercase SMI to Smi

Browse Source
This commit is contained in:
Howard Mao 2016-01-11 16:18:49 -08:00
parent 80d97d5f9e
commit 04e1f8c5c3
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
groundtest/src/main/scala/tile.scala
View File

@ -3,7 +3,7 @@ package groundtest
import Chisel._
import rocket._
import uncore._
import junctions.{SMIIO, ParameterizedBundle}
import junctions.{SmiIO, ParameterizedBundle}
import scala.util.Random
import cde.{Parameters, Field}
@ -81,7 +81,7 @@ class CSRHandler(implicit val p: Parameters) extends Module {
val io = new Bundle {
val finished = Bool(INPUT)
val csr = new SMIIO(csrDataBits, csrAddrBits).flip
val csr = new SmiIO(csrDataBits, csrAddrBits).flip
}
val csr_resp_valid = Reg(Bool()) // Don't reset