Howard Mao
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a9e0a5e2df
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changes to imports after uncore refactor
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2016-06-28 14:09:31 -07:00 |
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Andrew Waterman
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60bddddfe6
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Merge sptbr and sasid
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2016-06-17 18:29:05 -07:00 |
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Andrew Waterman
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586c1079d0
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Fix D$ for set size > page size
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2016-06-09 13:02:28 -07:00 |
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Andrew Waterman
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51379621d6
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Flush blocking D$ on FENCE.I
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2016-05-31 19:27:28 -07:00 |
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Andrew Waterman
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40f38dde63
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Work around lack of zero-width wires in D$
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2016-05-25 19:44:31 -07:00 |
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Andrew Waterman
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4605b616c1
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Fix bug in D$ AMO/storegen logic
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2016-05-24 16:26:07 -07:00 |
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Andrew Waterman
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5dac7b818d
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Support set associativity in blocking D$
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2016-05-24 15:45:52 -07:00 |
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Andrew Waterman
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e0addb5723
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Support uncached AMOs in blocking D$
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2016-05-24 15:45:35 -07:00 |
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Andrew Waterman
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3b35c7470e
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Add uncached support to blocking D$
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2016-05-24 15:05:41 -07:00 |
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Andrew Waterman
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b92c73e361
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Add LR/SC to blocking D$
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2016-05-24 15:05:41 -07:00 |
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Andrew Waterman
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0d93d1a1a0
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Clean up pending store logic a bit
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2016-05-24 15:05:41 -07:00 |
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Andrew Waterman
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0b8de578d4
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Add additional D$ store buffering to prevent structural hazards
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2016-05-24 15:05:41 -07:00 |
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Andrew Waterman
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d7790ac6a4
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WIP on blocking D$
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2016-05-24 15:05:41 -07:00 |
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Andrew Waterman
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7bc38383de
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add (non-working) blocking data cache
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2016-05-20 18:59:05 -07:00 |
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Andrew Waterman
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25ecfb9bbc
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clean up caches
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
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2012-02-12 20:32:06 -08:00 |
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Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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Christopher Celio
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1be9d15944
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Fixed bug regarding case sensitivity regarding ioICache,ioDCache
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2012-02-07 14:07:42 -08:00 |
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Andrew Waterman
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a5a020f97b
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update chisel and remove SRAM_READ_LATENCY
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2012-01-23 20:59:38 -08:00 |
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Henry Cook
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8766438bb9
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Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
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2012-01-23 17:09:23 -08:00 |
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Henry Cook
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7e25749581
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Groundwork for assoc cache implementation
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2012-01-18 17:09:35 -08:00 |
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Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
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2012-01-18 14:39:57 -08:00 |
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Andrew Waterman
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ffe23a1ee8
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fix WAW hazard handling
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2012-01-02 00:25:11 -08:00 |
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Andrew Waterman
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a8d0cd95e6
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hellacache now works
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2011-12-17 03:26:11 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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8308345364
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work in progress on hellacache
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2011-12-10 07:01:47 -08:00 |
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Andrew Waterman
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ce201559f3
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Support cache->cpu nacks one cycle after request
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2011-12-10 00:42:09 -08:00 |
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Andrew Waterman
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c01e1f1cef
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Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
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2011-12-09 19:42:58 -08:00 |
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Andrew Waterman
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218f63e66e
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code cleanup/parameterization
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2011-12-09 00:42:43 -08:00 |
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Rimas Avizienis
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fa784d1d7d
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made setReadLatency argument a parameter defined in consts.scala
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2011-12-05 00:33:17 -08:00 |
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Rimas Avizienis
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ff95cacb55
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icache/dcache tag+data arrays now implemented using Mem4()
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
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2011-12-04 01:18:38 -08:00 |
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Rimas Avizienis
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e894b79870
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caches now use Mem4() memories for tag+data arrays
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2011-12-03 19:41:15 -08:00 |
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Rimas Avizienis
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c580180b66
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tweaks to cache/SRAM interface for TSMC65 SRAMs
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2011-12-02 02:01:08 -08:00 |
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Rimas Avizienis
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cf1965493b
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renamed SRAM modules to match TSMC65 MC generated SRAMs
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2011-12-01 13:14:33 -08:00 |
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Rimas Avizienis
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c42d8149b7
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moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
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2011-11-17 23:50:45 -08:00 |
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Rimas Avizienis
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80b4253318
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fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
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2011-11-16 02:04:28 -08:00 |
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Rimas Avizienis
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82a636ff55
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AMOADD, AMOAND, AMOOR, AMOSWAP working
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2011-11-15 00:51:45 -08:00 |
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Rimas Avizienis
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48cec01710
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updated riscv-bmarks and riscv-tests to build with new toolchain
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2011-11-15 00:11:22 -08:00 |
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Rimas Avizienis
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9d3471a569
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more cache fixes, more test harness debug output
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2011-11-13 23:32:18 -08:00 |
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Rimas Avizienis
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67c7e7e28f
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cache/tlb bugfixes, increased memory size to 256meg
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2011-11-13 13:06:35 -08:00 |
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Rimas Avizienis
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5f4b15b809
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added ld/st misaligned exceptions
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2011-11-13 00:03:17 -08:00 |
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Rimas Avizienis
|
35af912bd2
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cache optimizations, cleanup, and testharness improvement
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2011-11-12 22:13:29 -08:00 |
|
Rimas Avizienis
|
91c252ad08
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fixing output enable signals for data/tag SRAMs
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2011-11-12 15:47:47 -08:00 |
|
Rimas Avizienis
|
83d90c4dab
|
more itlb/dtlb/ptw fixes
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2011-11-12 15:00:45 -08:00 |
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Rimas Avizienis
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73416f224b
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more tlb/ptw debugging
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2011-11-12 00:25:06 -08:00 |
|
Rimas Avizienis
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a1ce908541
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dcache/dtlb overhaul
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2011-11-11 18:18:47 -08:00 |
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Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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9aca403aa8
|
more itlb integration & cleanup
|
2011-11-09 23:18:14 -08:00 |
|
Rimas Avizienis
|
e96430d862
|
integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
|
Rimas Avizienis
|
9d63087eb2
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changed caches to use separate sram modules for tag and data arrays
|
2011-11-07 00:58:25 -08:00 |
|
Rimas Avizienis
|
4d64099103
|
cleanup
|
2011-11-04 20:52:21 -07:00 |
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