518 lines
19 KiB
Scala
518 lines
19 KiB
Scala
package Top {
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import Chisel._
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import Node._;
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import Constants._;
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import scala.math._;
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// interface between D$ and processor/DTLB
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class ioDmem(view: List[String] = null) extends Bundle(view) {
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val req_kill = Bool(INPUT);
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val req_val = Bool(INPUT);
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val req_rdy = Bool(OUTPUT);
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val req_cmd = Bits(4, INPUT);
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val req_type = Bits(3, INPUT);
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val req_idx = Bits(PGIDX_BITS, INPUT);
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val req_ppn = Bits(PPN_BITS, INPUT);
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val req_data = Bits(64, INPUT);
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val req_tag = Bits(DCACHE_TAG_BITS, INPUT);
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val xcpt_ma_ld = Bool(OUTPUT); // misaligned load
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val xcpt_ma_st = Bool(OUTPUT); // misaligned store
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val resp_miss = Bool(OUTPUT);
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val resp_nack = Bool(OUTPUT);
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val resp_val = Bool(OUTPUT);
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val resp_replay = Bool(OUTPUT);
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val resp_data = Bits(64, OUTPUT);
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val resp_data_subword = Bits(64, OUTPUT);
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val resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT);
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}
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// interface between D$ and next level in memory hierarchy
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class ioDCache(view: List[String] = null) extends Bundle(view) {
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val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
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val req_tag = UFix(DMEM_TAG_BITS, INPUT);
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val req_val = Bool(INPUT);
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val req_rdy = Bool(OUTPUT);
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val req_wdata = Bits(MEM_DATA_BITS, INPUT);
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val req_rw = Bool(INPUT);
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val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
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val resp_tag = Bits(DMEM_TAG_BITS, OUTPUT);
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val resp_val = Bool(OUTPUT);
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}
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class ioDCacheDM extends Bundle() {
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val cpu = new ioDmem();
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val mem = new ioDCache().flip();
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}
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class ioDCacheHella extends Bundle() {
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val cpu = new ioDmem();
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val mem = new ioDCache().flip();
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}
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class rocketDCacheStoreGen extends Component {
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val io = new Bundle {
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val req_type = Bits(3, INPUT);
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val req_addr_lsb = Bits(3, INPUT);
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val req_data = Bits(64, INPUT);
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val store_wmask = Bits(64, OUTPUT);
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val store_data = Bits(64, OUTPUT);
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}
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// generate write mask and store data signals based on store type and address LSBs
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val wmask_b =
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Mux(io.req_addr_lsb === UFix(0, 3), Bits("b0000_0001", 8),
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Mux(io.req_addr_lsb === UFix(1, 3), Bits("b0000_0010", 8),
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Mux(io.req_addr_lsb === UFix(2, 3), Bits("b0000_0100", 8),
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Mux(io.req_addr_lsb === UFix(3, 3), Bits("b0000_1000", 8),
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Mux(io.req_addr_lsb === UFix(4, 3), Bits("b0001_0000", 8),
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Mux(io.req_addr_lsb === UFix(5, 3), Bits("b0010_0000", 8),
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Mux(io.req_addr_lsb === UFix(6, 3), Bits("b0100_0000", 8),
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Mux(io.req_addr_lsb === UFix(7, 3), Bits("b1000_0000", 8),
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UFix(0, 8)))))))));
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val wmask_h =
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Mux(io.req_addr_lsb(2,1) === UFix(0, 2), Bits("b0000_0011", 8),
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Mux(io.req_addr_lsb(2,1) === UFix(1, 2), Bits("b0000_1100", 8),
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Mux(io.req_addr_lsb(2,1) === UFix(2, 2), Bits("b0011_0000", 8),
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Mux(io.req_addr_lsb(2,1) === UFix(3, 2), Bits("b1100_0000", 8),
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UFix(0, 8)))));
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val wmask_w =
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Mux(io.req_addr_lsb(2) === UFix(0, 1), Bits("b0000_1111", 8),
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Mux(io.req_addr_lsb(2) === UFix(1, 1), Bits("b1111_0000", 8),
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UFix(0, 8)));
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val wmask_d =
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Bits("b1111_1111", 8);
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val store_wmask_byte =
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Mux(io.req_type === MT_B, wmask_b,
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Mux(io.req_type === MT_H, wmask_h,
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Mux(io.req_type === MT_W, wmask_w,
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Mux(io.req_type === MT_D, wmask_d,
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UFix(0, 8)))));
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val store_wmask_d = Cat(Fill(8, store_wmask_byte(7)),
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Fill(8, store_wmask_byte(6)),
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Fill(8, store_wmask_byte(5)),
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Fill(8, store_wmask_byte(4)),
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Fill(8, store_wmask_byte(3)),
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Fill(8, store_wmask_byte(2)),
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Fill(8, store_wmask_byte(1)),
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Fill(8, store_wmask_byte(0)));
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io.store_wmask := store_wmask_d;
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io.store_data :=
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Mux(io.req_type === MT_B, Fill(8, io.req_data( 7,0)),
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Mux(io.req_type === MT_H, Fill(4, io.req_data(15,0)),
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Mux(io.req_type === MT_W, Fill(2, io.req_data(31,0)),
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Mux(io.req_type === MT_D, io.req_data,
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UFix(0, 64)))));
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}
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// state machine to flush (write back dirty lines, invalidate clean ones) the D$
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class rocketDCacheDM_flush(lines: Int) extends Component {
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val io = new ioDCacheDM();
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val dcache = new rocketDCacheDM(lines);
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val addrbits = PADDR_BITS;
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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val offsetbits = 6;
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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val tagbits = tagmsb-taglsb+1;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 3;
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val flush_count = Reg(resetVal = UFix(0, indexbits));
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val flush_resp_count = Reg(resetVal = UFix(0, indexbits));
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val flushing = Reg(resetVal = Bool(false));
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val flush_waiting = Reg(resetVal = Bool(false));
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val r_cpu_req_tag = Reg() { Bits() }
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when (io.cpu.req_val && io.cpu.req_rdy && (io.cpu.req_cmd === M_FLA))
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{
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r_cpu_req_tag <== io.cpu.req_tag;
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flushing <== Bool(true);
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flush_waiting <== Bool(true);
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}
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when (dcache.io.cpu.req_rdy && (flush_count === ~Bits(0, indexbits))) {
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flushing <== Bool(false);
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}
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when (dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag === r_cpu_req_tag) && (flush_resp_count === ~Bits(0, indexbits))) {
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flush_waiting <== Bool(false);
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}
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when (flushing && dcache.io.cpu.req_rdy) {
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flush_count <== flush_count + UFix(1,1);
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}
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when (flush_waiting && dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag === r_cpu_req_tag)) {
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flush_resp_count <== flush_resp_count + UFix(1,1);
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}
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dcache.io.cpu.req_val := (io.cpu.req_val && (io.cpu.req_cmd != M_FLA) && !flush_waiting) || flushing;
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dcache.io.cpu.req_cmd := Mux(flushing, M_FLA, io.cpu.req_cmd);
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dcache.io.cpu.req_idx := Mux(flushing, Cat(flush_count, Bits(0,offsetbits)), io.cpu.req_idx);
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dcache.io.cpu.req_ppn := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn);
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dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
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dcache.io.cpu.req_type := io.cpu.req_type;
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dcache.io.cpu.req_data <> io.cpu.req_data;
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dcache.io.cpu.req_kill := io.cpu.req_kill && !flush_waiting;
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dcache.io.mem <> io.mem;
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io.cpu.xcpt_ma_ld := dcache.io.cpu.xcpt_ma_ld;
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io.cpu.xcpt_ma_st := dcache.io.cpu.xcpt_ma_st;
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io.cpu.req_rdy := dcache.io.cpu.req_rdy && !flush_waiting;
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io.cpu.resp_miss := dcache.io.cpu.resp_miss;
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io.cpu.resp_nack := dcache.io.cpu.resp_nack;
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io.cpu.resp_data := dcache.io.cpu.resp_data;
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io.cpu.resp_tag := dcache.io.cpu.resp_tag;
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io.cpu.resp_val := dcache.io.cpu.resp_val &
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!(flush_waiting && (io.cpu.resp_tag === r_cpu_req_tag) && (flush_count != ~Bits(0, addrbits)));
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}
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class rocketDCacheDM(lines: Int) extends Component {
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val io = new ioDCacheDM();
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val addrbits = PADDR_BITS;
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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val offsetbits = 6; // 64 byte cache lines = 2^6 bytes
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val tagmsb = PADDR_BITS-1;
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val taglsb = indexbits+offsetbits;
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val tagbits = tagmsb-taglsb+1;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 3;
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val s_reset :: s_ready :: s_replay_load :: s_write_amo :: s_start_writeback :: s_writeback :: s_req_refill :: s_refill :: s_resolve_miss :: Nil = Enum(9) { UFix() };
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val state = Reg(resetVal = s_reset);
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// idx arrives one clock cycle prior to ppn b/c of DTLB
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val r_cpu_req_idx = Reg(resetVal = Bits(0, PGIDX_BITS));
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val r_cpu_req_ppn = Reg(resetVal = Bits(0, PPN_BITS));
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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val r_cpu_req_cmd = Reg(resetVal = Bits(0,4));
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val r_cpu_req_type = Reg(resetVal = Bits(0,3));
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val r_cpu_req_tag = Reg() { Bits() }
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val r_cpu_resp_val = Reg(resetVal = Bool(false));
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val r_amo_data = Reg(resetVal = Bits(0,64));
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val p_store_data = Reg(resetVal = Bits(0,64));
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val p_store_idx = Reg(resetVal = Bits(0,PGIDX_BITS));
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val p_store_type = Reg(resetVal = Bits(0,3));
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val p_store_valid = Reg(resetVal = Bool(false));
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val req_store = (io.cpu.req_cmd === M_XWR);
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val req_load = (io.cpu.req_cmd === M_XRD);
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val req_flush = (io.cpu.req_cmd === M_FLA);
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val req_amo = io.cpu.req_cmd(3).toBool;
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val r_req_load = (r_cpu_req_cmd === M_XRD);
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val r_req_store = (r_cpu_req_cmd === M_XWR);
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val r_req_flush = (r_cpu_req_cmd === M_FLA);
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val r_req_amo = r_cpu_req_cmd(3).toBool;
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when (io.cpu.req_val && io.cpu.req_rdy) {
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r_cpu_req_idx <== io.cpu.req_idx;
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r_cpu_req_cmd <== io.cpu.req_cmd;
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r_cpu_req_type <== io.cpu.req_type;
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r_cpu_req_tag <== io.cpu.req_tag;
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}
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when ((state === s_ready) && r_cpu_req_val && !io.cpu.req_kill) {
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r_cpu_req_ppn <== io.cpu.req_ppn;
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}
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when (io.cpu.req_rdy) {
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r_cpu_req_val <== io.cpu.req_val;
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}
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otherwise {
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r_cpu_req_val <== Bool(false);
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}
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when (((state === s_resolve_miss) && (r_req_load || r_req_amo)) || (state === s_replay_load)) {
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r_cpu_resp_val <== Bool(true);
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}
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otherwise {
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r_cpu_resp_val <== Bool(false);
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}
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// refill counter
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val rr_count = Reg(resetVal = UFix(0,2));
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val rr_count_next = rr_count + UFix(1);
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when (((state === s_refill) && io.mem.resp_val) || ((state === s_writeback) && io.mem.req_rdy)) {
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rr_count <== rr_count_next;
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}
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// tag array
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val tag_addr =
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Mux((state === s_ready), io.cpu.req_idx(PGIDX_BITS-1,offsetbits),
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r_cpu_req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
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val tag_we =
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((state === s_refill) && io.mem.resp_val && (rr_count === UFix(3,2))) ||
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((state === s_resolve_miss) && r_req_flush);
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val tag_array = Mem4(lines, r_cpu_req_ppn);
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tag_array.setReadLatency(1);
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tag_array.setTarget('inst);
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val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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when (tag_we && !r_req_flush) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (tag_we && r_req_flush) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
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}
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val vb_rdata = vb_array(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix).toBool;
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val tag_valid = r_cpu_req_val && vb_rdata;
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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val tag_hit = tag_valid && tag_match;
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val miss = r_cpu_req_val && (!vb_rdata || !tag_match);
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// load/store addresses conflict if they are to any part of the same 64 bit word
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val addr_match = (r_cpu_req_idx(PGIDX_BITS-1,offsetlsb) === p_store_idx(PGIDX_BITS-1,offsetlsb));
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val ldst_conflict = tag_valid && tag_match && (r_req_load || r_req_amo) && p_store_valid && addr_match;
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val store_hit = r_cpu_req_val && !io.cpu.req_kill && tag_hit && r_req_store ;
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// write the pending store data when the cache is idle, when the next command isn't a load
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// or when there's a load to the same address (in which case there's a 2 cycle delay:
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// once cycle to write the store data and another to read the data back)
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val drain_store =
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((store_hit || p_store_valid) && (!io.cpu.req_val || req_store || req_flush)) ||
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(p_store_valid && (miss || ldst_conflict));
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// write pending store data from a store which missed
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// after the cache line refill has completed
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val resolve_store = (state === s_resolve_miss) && r_req_store;
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// pending store data
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when (io.cpu.req_val && io.cpu.req_rdy && req_store) {
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p_store_idx <== io.cpu.req_idx;
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p_store_data <== io.cpu.req_data;
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p_store_type <== io.cpu.req_type;
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}
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when (store_hit && !drain_store) {
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p_store_valid <== Bool(true);
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}
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when (drain_store) {
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p_store_valid <== Bool(false);
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}
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// AMO operand
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when (io.cpu.req_val && io.cpu.req_rdy && req_amo) {
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r_amo_data <== io.cpu.req_data;
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}
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// dirty bit array
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val db_array = Reg(resetVal = Bits(0, lines));
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val tag_dirty = db_array(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix).toBool;
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when ((r_cpu_req_val && !io.cpu.req_kill && tag_hit && r_req_store) || resolve_store) {
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db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (state === s_write_amo) {
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db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (tag_we) {
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db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
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}
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// generate write mask and data signals for stores and amos
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val storegen = new rocketDCacheStoreGen();
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storegen.io.req_addr_lsb := p_store_idx(2,0);
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storegen.io.req_data := p_store_data;
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storegen.io.req_type := p_store_type;
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val store_data = Fill(2, storegen.io.store_data);
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val store_wmask_d = storegen.io.store_wmask;
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val store_wmask = Mux(p_store_idx(offsetlsb).toBool, Cat(store_wmask_d, Bits(0,64)), Cat(Bits(0,64), store_wmask_d));
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// ALU for AMOs
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val amo_alu = new rocketDCacheAmoALU();
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val amo_alu_out = Cat(amo_alu.io.result,amo_alu.io.result);
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val amo_wmask =
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Mux(r_cpu_req_type === MT_D, ~Bits(0,8),
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Mux(r_cpu_req_idx(2).toBool, Cat(~Bits(0,4), Bits(0,4)),
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Cat(Bits(0,4), ~Bits(0,4))));
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val amo_store_wmask_d = Cat(Fill(8, amo_wmask(7)),
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Fill(8, amo_wmask(6)),
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Fill(8, amo_wmask(5)),
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Fill(8, amo_wmask(4)),
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Fill(8, amo_wmask(3)),
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Fill(8, amo_wmask(2)),
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Fill(8, amo_wmask(1)),
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Fill(8, amo_wmask(0)));
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val amo_store_wmask = Mux(r_cpu_req_idx(offsetlsb).toBool, Cat(amo_store_wmask_d, Bits(0,64)), Cat(Bits(0,64), amo_store_wmask_d));
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// data array
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val data_addr =
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Mux(drain_store || resolve_store, p_store_idx(PGIDX_BITS-1, offsetmsb-1),
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Mux((state === s_writeback) && io.mem.req_rdy, Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count_next),
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Mux((state === s_start_writeback) || (state === s_writeback) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count),
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Mux((state === s_resolve_miss) || (state === s_replay_load) || (state === s_write_amo), r_cpu_req_idx(PGIDX_BITS-1, offsetmsb-1),
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io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1))))).toUFix;
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val data_wdata =
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Mux((state === s_refill), io.mem.resp_data,
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Mux((state === s_write_amo), amo_alu_out,
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store_data));
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val data_we =
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((state === s_refill) && io.mem.resp_val) ||
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(state === s_write_amo) ||
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drain_store || resolve_store;
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val data_wmask =
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Mux((state === s_refill), ~Bits(0,128),
|
|
Mux((state === s_write_amo), amo_store_wmask,
|
|
store_wmask));
|
|
|
|
val data_array = Mem4(lines*4, data_wdata);
|
|
data_array.setReadLatency(1);
|
|
data_array.setTarget('inst);
|
|
val data_array_rdata = data_array.rw(data_addr, data_wdata, data_we, data_wmask);
|
|
val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
|
|
val r_resp_data = Reg(resp_data);
|
|
|
|
amo_alu.io.cmd := r_cpu_req_cmd;
|
|
amo_alu.io.wmask := amo_wmask;
|
|
amo_alu.io.lhs := Mux(r_cpu_resp_val, resp_data, r_resp_data).toUFix;
|
|
amo_alu.io.rhs := r_amo_data.toUFix;
|
|
|
|
// signal a load miss when the data isn't present in the cache and when it's in the pending store data register
|
|
// (causes the cache to block for 2 cycles and the load or amo instruction is replayed)
|
|
val load_miss =
|
|
!io.cpu.req_kill &&
|
|
(state === s_ready) && r_cpu_req_val && (r_req_load || r_req_amo) && (!tag_hit || (p_store_valid && addr_match));
|
|
|
|
// output signals
|
|
// busy when there's a load to the same address as a pending store, or on a cache miss, or when executing a flush
|
|
io.cpu.req_rdy := (state === s_ready) && !io.cpu.req_kill && !ldst_conflict && (!r_cpu_req_val || (tag_hit && !(r_req_flush || r_req_amo)));
|
|
io.cpu.resp_val := !io.cpu.req_kill &&
|
|
((state === s_ready) && tag_hit && (r_req_load || r_req_amo) && !(p_store_valid && addr_match)) ||
|
|
((state === s_resolve_miss) && r_req_flush) ||
|
|
r_cpu_resp_val;
|
|
|
|
val misaligned =
|
|
(((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && r_cpu_req_idx(0).toBool) ||
|
|
(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
|
|
((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
|
|
|
|
io.cpu.xcpt_ma_ld := r_cpu_req_val && (r_req_load || r_req_amo) && misaligned;
|
|
io.cpu.xcpt_ma_st := r_cpu_req_val && (r_req_store || r_req_amo) && misaligned;
|
|
|
|
io.cpu.resp_miss := load_miss;
|
|
io.cpu.resp_nack := Bool(false)
|
|
io.cpu.resp_tag := r_cpu_req_tag
|
|
io.cpu.resp_data := resp_data;
|
|
|
|
io.mem.req_val := (state === s_req_refill) || (state === s_writeback);
|
|
io.mem.req_rw := (state === s_writeback);
|
|
io.mem.req_wdata := data_array_rdata;
|
|
io.mem.req_tag := UFix(0);
|
|
io.mem.req_addr :=
|
|
Mux(state === s_writeback, Cat(tag_rdata, r_cpu_req_idx(PGIDX_BITS-1, offsetbits)),
|
|
Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits))).toUFix;
|
|
|
|
// control state machine
|
|
switch (state) {
|
|
is (s_reset) {
|
|
state <== s_ready;
|
|
}
|
|
is (s_ready) {
|
|
when (io.cpu.req_kill) {
|
|
state <== s_ready;
|
|
}
|
|
when (ldst_conflict) {
|
|
state <== s_replay_load;
|
|
}
|
|
when (!r_cpu_req_val || (tag_hit && !(r_req_flush || r_req_amo))) {
|
|
state <== s_ready;
|
|
}
|
|
when (tag_hit && r_req_amo) {
|
|
state <== s_write_amo;
|
|
}
|
|
when (tag_valid & tag_dirty) {
|
|
state <== s_start_writeback;
|
|
}
|
|
when (r_req_flush) {
|
|
state <== s_resolve_miss;
|
|
}
|
|
otherwise {
|
|
state <== s_req_refill;
|
|
}
|
|
}
|
|
is (s_replay_load) {
|
|
state <== s_ready;
|
|
}
|
|
is (s_write_amo) {
|
|
state <== s_ready;
|
|
}
|
|
is (s_start_writeback) {
|
|
state <== s_writeback;
|
|
}
|
|
is (s_writeback) {
|
|
when (io.mem.req_rdy && (rr_count === UFix(3,2))) {
|
|
when (r_req_flush) {
|
|
state <== s_resolve_miss;
|
|
}
|
|
otherwise {
|
|
state <== s_req_refill;
|
|
}
|
|
}
|
|
}
|
|
is (s_req_refill)
|
|
{
|
|
when (io.mem.req_rdy) { state <== s_refill; }
|
|
}
|
|
is (s_refill) {
|
|
when (io.mem.resp_val && (rr_count === UFix(3,2))) { state <== s_resolve_miss; }
|
|
}
|
|
is (s_resolve_miss) {
|
|
when (r_req_amo) {
|
|
state <== s_write_amo;
|
|
}
|
|
state <== s_ready;
|
|
}
|
|
}
|
|
}
|
|
|
|
class rocketDCacheAmoALU extends Component {
|
|
val io = new Bundle {
|
|
val cmd = Bits(4, INPUT);
|
|
val wmask = Bits(8, INPUT);
|
|
val lhs = UFix(64, INPUT);
|
|
val rhs = UFix(64, INPUT);
|
|
val result = UFix(64, OUTPUT);
|
|
}
|
|
|
|
// val signed_cmp = (op === M_XA_MIN) || (op === M_XA_MAX);
|
|
// val sub = (op === M_XA_MIN) || (op === M_XA_MINU) ||
|
|
// (op === M_XA_MAX) || (op === M_XA_MAXU);
|
|
|
|
val adder_lhs = Cat(io.lhs(63,32),io.wmask(3) & io.lhs(31), io.lhs(30,0)).toUFix;
|
|
val adder_rhs = Cat(io.rhs(63,32),io.wmask(3) & io.rhs(31), io.rhs(30,0)).toUFix;
|
|
// val adder_rhs = Cat(Mux(sub, ~io.rhs, io.rhs), sub).toUFix;
|
|
// val sum = adder_lhs + adder_rhs;
|
|
// val adder_out = sum(64,1);
|
|
val adder_out = adder_lhs + adder_rhs;
|
|
val alu_out = Wire() { UFix() };
|
|
switch (io.cmd) {
|
|
// is (M_XA_ADD) { alu_out <== adder_out; }
|
|
is (M_XA_SWAP) { alu_out <== io.rhs; }
|
|
is (M_XA_AND) { alu_out <== io.lhs & io.rhs; }
|
|
is (M_XA_OR) { alu_out <== io.lhs | io.rhs; }
|
|
}
|
|
alu_out <== adder_out;
|
|
io.result := alu_out;
|
|
}
|
|
|
|
}
|