423 lines
16 KiB
Scala
423 lines
16 KiB
Scala
package Top {
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import Chisel._
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import Node._;
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import Constants._;
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import scala.math._;
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// interface between D$ and processor/DTLB
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class ioDmem(view: List[String] = null) extends Bundle(view) {
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// val dtlb_busy = Bool('input);
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val dtlb_miss = Bool('input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val req_cmd = Bits(4, 'input);
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val req_type = Bits(3, 'input);
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val req_idx = Bits(PGIDX_BITS, 'input);
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val req_ppn = Bits(PPN_BITS, 'input);
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// val req_addr = UFix(PADDR_BITS, 'input);
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val req_data = Bits(64, 'input);
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val req_tag = Bits(5, 'input);
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val resp_miss = Bool('output);
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val resp_val = Bool('output);
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val resp_data = Bits(64, 'output);
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val resp_tag = Bits(12, 'output);
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}
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// interface between D$ and next level in memory hierarchy
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class ioDcache(view: List[String] = null) extends Bundle(view) {
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val req_addr = UFix(PADDR_BITS, 'input);
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val req_tag = UFix(3, 'input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val req_wdata = Bits(128, 'input);
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val req_rw = Bool('input);
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val resp_data = Bits(128, 'output);
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// val resp_tag = Bits(3, 'output);
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val resp_val = Bool('output);
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}
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class ioDCacheDM extends Bundle() {
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val cpu = new ioDmem();
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val mem = new ioDcache().flip();
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}
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class rocketDCacheStoreGen extends Component {
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val io = new Bundle {
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val req_type = Bits(3, 'input);
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val req_addr_lsb = Bits(3, 'input);
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val req_data = Bits(64, 'input);
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val store_wmask = Bits(64, 'output);
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val store_data = Bits(64, 'output);
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}
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// generate write mask and store data signals based on store type and address LSBs
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val wmask_b =
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Mux(io.req_addr_lsb === UFix(0, 3), Bits("b0000_0001", 8),
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Mux(io.req_addr_lsb === UFix(1, 3), Bits("b0000_0010", 8),
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Mux(io.req_addr_lsb === UFix(2, 3), Bits("b0000_0100", 8),
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Mux(io.req_addr_lsb === UFix(3, 3), Bits("b0000_1000", 8),
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Mux(io.req_addr_lsb === UFix(4, 3), Bits("b0001_0000", 8),
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Mux(io.req_addr_lsb === UFix(5, 3), Bits("b0010_0000", 8),
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Mux(io.req_addr_lsb === UFix(6, 3), Bits("b0100_0000", 8),
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Mux(io.req_addr_lsb === UFix(7, 3), Bits("b1000_0000", 8),
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UFix(0, 8)))))))));
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val wmask_h =
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Mux(io.req_addr_lsb(2,1) === UFix(0, 2), Bits("b0000_0011", 8),
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Mux(io.req_addr_lsb(2,1) === UFix(1, 2), Bits("b0000_1100", 8),
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Mux(io.req_addr_lsb(2,1) === UFix(2, 2), Bits("b0011_0000", 8),
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Mux(io.req_addr_lsb(2,1) === UFix(3, 2), Bits("b1100_0000", 8),
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UFix(0, 8)))));
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val wmask_w =
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Mux(io.req_addr_lsb(2) === UFix(0, 1), Bits("b0000_1111", 8),
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Mux(io.req_addr_lsb(2) === UFix(1, 1), Bits("b1111_0000", 8),
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UFix(0, 8)));
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val wmask_d =
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Bits("b1111_1111", 8);
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val store_wmask_byte =
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Mux(io.req_type === MT_B, wmask_b,
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Mux(io.req_type === MT_H, wmask_h,
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Mux(io.req_type === MT_W, wmask_w,
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Mux(io.req_type === MT_D, wmask_d,
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UFix(0, 8)))));
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io.store_wmask :=
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Cat(Fill(8, store_wmask_byte(7)),
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Fill(8, store_wmask_byte(6)),
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Fill(8, store_wmask_byte(5)),
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Fill(8, store_wmask_byte(4)),
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Fill(8, store_wmask_byte(3)),
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Fill(8, store_wmask_byte(2)),
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Fill(8, store_wmask_byte(1)),
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Fill(8, store_wmask_byte(0)));
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io.store_data :=
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Mux(io.req_type === MT_B, Fill(8, io.req_data( 7,0)),
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Mux(io.req_type === MT_H, Fill(4, io.req_data(15,0)),
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Mux(io.req_type === MT_W, Fill(2, io.req_data(31,0)),
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Mux(io.req_type === MT_D, io.req_data,
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UFix(0, 64)))));
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}
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// state machine to flush (write back dirty lines, invalidate clean ones) the D$
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class rocketDCacheDM_flush(lines: Int) extends Component {
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val io = new ioDCacheDM();
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val dcache = new rocketDCacheDM(lines);
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val addrbits = PADDR_BITS;
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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val offsetbits = 6;
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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val tagbits = tagmsb-taglsb+1;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 3;
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val flush_count = Reg(resetVal = UFix(0, indexbits));
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val flush_resp_count = Reg(resetVal = UFix(0, indexbits));
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val flushing = Reg(resetVal = Bool(false));
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val flush_waiting = Reg(resetVal = Bool(false));
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val r_cpu_req_tag = Reg(resetVal = Bits(0, 5));
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when (io.cpu.req_val && io.cpu.req_rdy && (io.cpu.req_cmd === M_FLA))
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{
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r_cpu_req_tag <== io.cpu.req_tag;
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flushing <== Bool(true);
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flush_waiting <== Bool(true);
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}
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when (dcache.io.cpu.req_rdy && (flush_count === ~Bits(0, indexbits))) {
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flushing <== Bool(false);
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}
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when (dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag === r_cpu_req_tag) && (flush_resp_count === ~Bits(0, indexbits))) {
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flush_waiting <== Bool(false);
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}
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when (flushing && dcache.io.cpu.req_rdy) {
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flush_count <== flush_count + UFix(1,1);
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}
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when (flush_waiting && dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag(5,0) === r_cpu_req_tag)) {
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flush_resp_count <== flush_resp_count + UFix(1,1);
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}
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dcache.io.cpu.req_val := (io.cpu.req_val && (io.cpu.req_cmd != M_FLA) && !flush_waiting) || flushing;
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dcache.io.cpu.req_cmd := Mux(flushing, M_FLA, io.cpu.req_cmd);
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dcache.io.cpu.req_idx := Mux(flushing, Cat(flush_count, Bits(0,offsetbits)), io.cpu.req_idx);
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dcache.io.cpu.req_ppn := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn);
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// dcache.io.cpu.req_addr :=
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// Mux(flushing, Cat(Bits(0,tagmsb-taglsb+1), flush_count, Bits(0,offsetbits)).toUFix,
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// io.cpu.req_addr);
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dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
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dcache.io.cpu.req_type := io.cpu.req_type;
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dcache.io.cpu.req_data ^^ io.cpu.req_data;
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// dcache.io.cpu.dtlb_busy := io.cpu.dtlb_busy;
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dcache.io.cpu.dtlb_miss := io.cpu.dtlb_miss;
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dcache.io.mem ^^ io.mem;
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io.cpu.req_rdy := dcache.io.cpu.req_rdy && !flush_waiting;
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io.cpu.resp_miss := dcache.io.cpu.resp_miss;
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io.cpu.resp_data := dcache.io.cpu.resp_data;
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io.cpu.resp_tag := dcache.io.cpu.resp_tag;
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io.cpu.resp_val := dcache.io.cpu.resp_val &
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!(flush_waiting && (io.cpu.resp_tag === r_cpu_req_tag) && (flush_count != ~Bits(0, addrbits)));
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}
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class rocketDCacheDM(lines: Int) extends Component {
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val io = new ioDCacheDM();
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val addrbits = PADDR_BITS;
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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val offsetbits = 6; // 64 byte cache lines = 2^6 bytes
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val tagmsb = PADDR_BITS-1;
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val taglsb = indexbits+offsetbits;
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val tagbits = tagmsb-taglsb+1;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 3;
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val s_reset :: s_ready :: s_replay_load :: s_start_writeback :: s_writeback :: s_req_refill :: s_refill :: s_resolve_miss :: Nil = Enum(8) { UFix() };
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val state = Reg(resetVal = s_reset);
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// idx arrives one clock cycle prior to ppn b/c of DTLB
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val r_cpu_req_idx = Reg(resetVal = Bits(0, PGIDX_BITS));
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val r_cpu_req_ppn = Reg(resetVal = Bits(0, PPN_BITS));
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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val r_cpu_req_cmd = Reg(resetVal = Bits(0,4));
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val r_cpu_req_type = Reg(resetVal = Bits(0,3));
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val r_cpu_req_tag = Reg(resetVal = Bits(0,5));
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val r_cpu_resp_val = Reg(resetVal = Bool(false));
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val p_store_data = Reg(resetVal = Bits(0,64));
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val p_store_idx = Reg(resetVal = Bits(0,PGIDX_BITS));
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val p_store_type = Reg(resetVal = Bits(0,3));
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val p_store_valid = Reg(resetVal = Bool(false));
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val req_store = (io.cpu.req_cmd === M_XWR);
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val req_load = (io.cpu.req_cmd === M_XRD) || (io.cpu.req_cmd === M_PRD);
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val r_req_load = (r_cpu_req_cmd === M_XRD) || (r_cpu_req_cmd === M_PRD);
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val r_req_store = (r_cpu_req_cmd === M_XWR);
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val r_req_flush = (r_cpu_req_cmd === M_FLA);
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val r_req_ptw_load = (r_cpu_req_cmd === M_PRD);
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when (io.cpu.req_val && io.cpu.req_rdy) {
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r_cpu_req_idx <== io.cpu.req_idx;
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r_cpu_req_cmd <== io.cpu.req_cmd;
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r_cpu_req_type <== io.cpu.req_type;
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r_cpu_req_tag <== io.cpu.req_tag;
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}
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when ((state === s_ready) && r_cpu_req_val && !io.cpu.dtlb_miss) {
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r_cpu_req_ppn <== io.cpu.req_ppn;
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}
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when (io.cpu.req_rdy) {
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r_cpu_req_val <== io.cpu.req_val;
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}
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otherwise {
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r_cpu_req_val <== Bool(false);
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}
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when (((state === s_resolve_miss) && r_req_load) || (state === s_replay_load)) {
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r_cpu_resp_val <== Bool(true);
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}
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otherwise {
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r_cpu_resp_val <== Bool(false);
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}
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// refill counter
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val rr_count = Reg(resetVal = UFix(0,2));
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val rr_count_next = rr_count + UFix(1);
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when (((state === s_refill) && io.mem.resp_val) || ((state === s_writeback) && io.mem.req_rdy)) {
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rr_count <== rr_count_next;
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}
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// tag array
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val tag_addr =
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Mux((state === s_ready), io.cpu.req_idx(PGIDX_BITS-1,offsetbits),
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r_cpu_req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
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val tag_we =
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((state === s_refill) && io.mem.req_rdy && (rr_count === UFix(3,2))) ||
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((state === s_resolve_miss) && r_req_flush);
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val tag_array = new rocketSRAMsp(lines, tagbits);
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tag_array.io.a := tag_addr;
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.we := tag_we;
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tag_array.io.bweb := ~Bits(0,tagbits);
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tag_array.io.ce := (state === s_ready) || (state === s_start_writeback) || (state === s_writeback);
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val tag_rdata = tag_array.io.q;
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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// val vb_rdata = Reg(vb_array(tag_raddr));
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when (tag_we && !r_req_flush) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (tag_we && r_req_flush) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
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}
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val vb_rdata = Reg(vb_array(tag_addr).toBool);
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val tag_valid = r_cpu_req_val && vb_rdata;
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// val tag_valid = Reg(vb_array(tag_addr)).toBool;
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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val addr_match = (r_cpu_req_idx(PGIDX_BITS-1,offsetbits) === p_store_idx(PGIDX_BITS-1,offsetbits));
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val ldst_conflict = r_cpu_req_val && r_req_load && p_store_valid && addr_match;
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// write the pending store data when the cache is idle, when the next command isn't a load
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// or when there's a load to the same address (in which case there's a 2 cycle delay:
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// once cycle to write the store data and another to read the data back)
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val drain_store = !io.cpu.dtlb_miss && p_store_valid && (!io.cpu.req_val || req_store || ldst_conflict);
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// write pending store data from a store which missed
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// after the cache line refill has completed
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val resolve_store = (state === s_resolve_miss) && r_req_store;
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// dirty bit array
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val db_array = Reg(resetVal = Bits(0, lines));
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// val db_rdata = Reg(db_array(tag_raddr));
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val tag_dirty = Reg(db_array(tag_addr)).toBool;
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when (io.cpu.req_val && io.cpu.req_rdy && req_store) {
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p_store_idx <== io.cpu.req_idx;
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p_store_data <== io.cpu.req_data;
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p_store_type <== io.cpu.req_type;
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p_store_valid <== Bool(true);
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}
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// cancel store if there's a DTLB miss
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when (r_cpu_req_val && r_req_store && io.cpu.dtlb_miss)
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{
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p_store_valid <== Bool(false);
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}
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when (drain_store) {
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p_store_valid <== Bool(false);
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db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (resolve_store) {
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db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (tag_we) {
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db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
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}
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// generate write mask and data signals for stores
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val storegen = new rocketDCacheStoreGen();
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storegen.io.req_addr_lsb := p_store_idx(2,0);
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storegen.io.req_data := p_store_data;
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storegen.io.req_type := p_store_type
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val store_data = Fill(2, storegen.io.store_data);
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val store_wmask_d = storegen.io.store_wmask;
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val store_idx_sel = p_store_idx(offsetlsb).toBool;
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val store_wmask = Mux(store_idx_sel, Cat(store_wmask_d, Bits(0,64)), Cat(Bits(0,64), store_wmask_d));
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// data array
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val data_array = new rocketSRAMsp(lines*4, 128);
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data_array.io.a :=
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Mux(drain_store || resolve_store, p_store_idx(PGIDX_BITS-1, offsetmsb-1),
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Mux((state === s_writeback) && io.mem.req_rdy, Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count_next),
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Mux((state === s_start_writeback) || (state === s_writeback) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count),
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Mux((state === s_resolve_miss) || (state === s_replay_load), r_cpu_req_idx(PGIDX_BITS-1, offsetmsb-1),
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io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1))))).toUFix;
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data_array.io.d := Mux((state === s_refill), io.mem.resp_data, store_data);
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data_array.io.we := ((state === s_refill) && io.mem.resp_val) || drain_store || resolve_store;
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data_array.io.bweb := Mux((state === s_refill), ~Bits(0,128), store_wmask);
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// data_array.io.ce := Bool(true); // FIXME
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data_array.io.ce :=
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(io.cpu.req_val && io.cpu.req_rdy && req_load) ||
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(state === s_start_writeback) ||
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(state === s_writeback) ||
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((state === s_resolve_miss) && r_req_load) ||
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(state === s_replay_load);
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val data_array_rdata = data_array.io.q;
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// signal a load miss when the data isn't present in the cache and when it's in the pending store data register
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// (causes the cache to block for 2 cycles and the load instruction is replayed)
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val hit = tag_valid && tag_match;
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val load_miss = !io.cpu.dtlb_miss && (state === s_ready) && r_cpu_req_val && r_req_load && (!hit || (p_store_valid && addr_match));
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// output signals
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// busy when there's a load to the same address as a pending store, or on a cache miss, or when executing a flush
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io.cpu.req_rdy := !io.cpu.dtlb_miss && (state === s_ready) && !ldst_conflict && (!r_cpu_req_val || (hit && !r_req_flush));
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io.cpu.resp_val := !io.cpu.dtlb_miss && ((state === s_ready) && hit && r_req_load && !(p_store_valid && addr_match)) ||
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((state === s_resolve_miss) && r_req_flush) ||
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r_cpu_resp_val;
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io.cpu.resp_miss := load_miss;
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// tag MSB distinguishes between loads destined for the PTW and CPU
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io.cpu.resp_tag := Cat(r_req_ptw_load, r_cpu_req_type, r_cpu_req_idx(2,0), r_cpu_req_tag);
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io.cpu.resp_data :=
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Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64),
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data_array_rdata(63,0));
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io.mem.req_val := (state === s_req_refill) || (state === s_writeback);
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io.mem.req_rw := (state === s_writeback);
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io.mem.req_wdata := data_array_rdata;
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io.mem.req_tag := UFix(0);
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io.mem.req_addr :=
|
|
Mux(state === s_writeback, Cat(tag_rdata, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count),
|
|
Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0,2))).toUFix;
|
|
|
|
// control state machine
|
|
switch (state) {
|
|
is (s_reset) {
|
|
state <== s_ready;
|
|
}
|
|
is (s_ready) {
|
|
when (io.cpu.dtlb_miss) {
|
|
state <== s_ready;
|
|
}
|
|
when (ldst_conflict) {
|
|
state <== s_replay_load;
|
|
}
|
|
when (!r_cpu_req_val || (hit && !r_req_flush)) {
|
|
state <== s_ready;
|
|
}
|
|
when (tag_valid & tag_dirty) {
|
|
state <== s_start_writeback;
|
|
}
|
|
when (r_req_flush) {
|
|
state <== s_resolve_miss;
|
|
}
|
|
otherwise {
|
|
state <== s_req_refill;
|
|
}
|
|
}
|
|
is (s_replay_load) {
|
|
state <== s_ready;
|
|
}
|
|
is (s_start_writeback) {
|
|
state <== s_writeback;
|
|
}
|
|
is (s_writeback) {
|
|
when (io.mem.req_rdy && (rr_count === UFix(3,2))) {
|
|
when (r_req_flush) {
|
|
state <== s_resolve_miss;
|
|
}
|
|
otherwise {
|
|
state <== s_req_refill;
|
|
}
|
|
}
|
|
}
|
|
is (s_req_refill)
|
|
{
|
|
when (io.mem.req_rdy) { state <== s_refill; }
|
|
}
|
|
is (s_refill) {
|
|
when (io.mem.resp_val && (rr_count === UFix(3,2))) { state <== s_resolve_miss; }
|
|
}
|
|
is (s_resolve_miss) {
|
|
state <== s_ready;
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|