riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao
77e859760c add a Hasti RAM alongside the Nasti ROM 2016-05-06 11:31:22 -07:00
Howard Mao
f26c422544 assert that TileLink router has valid route 2016-05-03 12:18:06 -07:00
Andrew Waterman
cc4102f8de Add trivial version of PRCI block 
It doesn't really do anything besides deliver deliver IPIs yet.
 2016-05-02 17:49:10 -07:00
Andrew Waterman
72731de25a Take a stab at the PRCI-Rocket interface 2016-05-02 15:20:33 -07:00
Andrew Waterman
695c4c5096 Support both Get and GetBlock on ROMSlave 2016-04-30 17:34:12 -07:00
Albert Ou
6f052a740c Add TileLink BRAM slave 2016-04-29 14:10:44 -07:00
Andrew Waterman
1df68a25fd Address Map refactoring 2016-04-28 16:08:58 -07:00
Wei Song
ed5bdf3c23 print the base address of each SCR as indicated 2016-04-28 16:31:56 +01:00
Andrew Waterman
81ff127dc3 Clean up TileLinkRecursiveInterconnect a bit 2016-04-27 14:53:11 -07:00
Andrew Waterman
87cecc336f Add new RTC as TileLink slave, not AXI master 2016-04-27 11:55:35 -07:00
Andrew Waterman
eb0b5ec61e Remove stats CSR 2016-04-27 00:16:21 -07:00
Andrew Waterman
9044a4a4b7 Replace NastiROM with ROMSlave, which uses TileLink 
I'm not wedded to the name.
 2016-04-27 00:15:30 -07:00
Andrew Waterman
356efe2fd5 Simplify TileLink Narrower 
It's not necessary to use addr_beat to determine where to put the Grant
data.  Just stripe it across all lanes.

This also gets rid of a dependence on addr_beat in Grant.  If we move
towards a regime where TileLink is only narrowed, not widened, we may
be able to drop the field altogether.
 2016-04-26 16:44:54 -07:00
Wei Song
f6e44b1348 avoid logical to physical header conversion overflow 2016-04-22 17:47:34 +01:00
Howard Mao
f9de99ed40 changes to match junctions no-mmio-base 2016-04-21 15:35:37 -07:00
Howard Mao
9b3faff5a5 add id field to write data channel in TL -> AXI converter 2016-04-19 09:46:31 -07:00
Howard Mao
152645b1bc use manager_id instead of client_id in GrantFromSrc and FinishToDst 2016-04-07 11:20:16 -07:00
Howard Mao
f88b6932ce don't add pending reads if data is already available 2016-04-06 15:43:21 -07:00
Howard Mao
31e145eaf0 fix BroadcastHub allocation and routing 2016-04-05 16:21:18 -07:00
Howard Mao
f68a7dabdf fix AXI -> TL converter 2016-04-04 19:42:25 -07:00
Howard Mao
f956d4edfb NASTI does not right-justify data; fix in converter 2016-04-01 20:55:00 -07:00
Henry Cook
c292a07ace Bugfix for merged voluntary releases in L2Cache. 
Track pending release beats for voluntary releases that are merged by Acquire Trackers.
Closes #23 and #24.
 2016-04-01 19:57:47 -07:00
Henry Cook
82bdf3afcb Fix LRSC starvation bug by punching Finish messages out to caching clients via a new TileLinkNetworkPort. 2016-04-01 16:17:27 -07:00
Andrew Waterman
8957b5e973 Improve simulation speed of BasicCrossbar 2016-04-01 13:28:11 -07:00
Howard Mao
3083bbca21 fix TileLink arbiters and add memory interconnect and memory selector 2016-03-31 18:15:51 -07:00
Howard Mao
cf363b1fe4 add TileLink interconnect generator 2016-03-31 14:12:55 -07:00
Howard Mao
d78066db5c chisel3 fix for split metadata 2016-03-30 22:11:19 -07:00
Howard Mao
3d990bdbef workaround for Chisel3 name-aliasing issue 2016-03-30 19:15:22 -07:00
Howard Mao
8e7f18084b switch RTC to use TileLink instead of AXI 2016-03-28 12:23:16 -07:00
Howard Mao
7f8f138d6a fix addPendingBitWhenPartialWritemask 2016-03-24 20:01:50 -07:00
Howard Mao
11bd15432a fix bug in RTC 2016-03-24 20:01:50 -07:00
Howard Mao
00b3908d92 git rid of reorder queue in narrower 2016-03-24 20:01:50 -07:00
Palmer Dabbelt
c6e974b110 Merge pull request #30 from ucb-bar/chisel3 
Chisel 3 support
 2016-03-24 11:52:02 -07:00
Palmer Dabbelt
c9e1b72972 Don't assign SInt(-1) to a UInt 2016-03-23 16:24:27 -07:00
Palmer Dabbelt
aa22f175c3 Add cloneType methods for Chisel3 2016-03-21 13:35:02 -07:00
Palmer Dabbelt
1344d09cef Fix the SCR file for Chisel 3 2016-03-21 11:55:18 -07:00
Henry Cook
c13b8d243d BroadcastHub race on allocating VolWBs vs Acquires 2016-03-17 18:32:35 -07:00
Henry Cook
5f3d3a0b2d Bugfix for probe flags in L2BroadcastHub 
Closes #25
 2016-03-17 16:42:40 -07:00
Henry Cook
49d82864bf Fix StoreDataQueue allocation bug in BroadcastHub 
Closes #27
 2016-03-17 12:31:18 -07:00
Eric Love
8a47c3f346 Make sure there's enough xact id bits 2016-03-16 13:49:30 -07:00
Henry Cook
67e711844a index extraction bug 2016-03-10 17:37:40 -08:00
Palmer Dabbelt
e2185d40f6 Avoid right-shift by larger that the bit width 
FIRRTL bails out on this.  There's an outstanding bug, this is just a
workaround.  See https://github.com/ucb-bar/firrtl/issues/69
 2016-03-10 17:37:40 -08:00
Palmer Dabbelt
8c7e29eacd Avoid generating 0-width UInts 
Chisel3 requires a 1-bit width to represent UInt(0).
 2016-03-10 17:37:40 -08:00
Andrew Waterman
2eafc4c8f3 Extend AMOALU to support RV32 2016-03-10 17:32:23 -08:00
Andrew Waterman
c28d115b30 Chisel3 compatibility fix 2016-03-10 17:32:23 -08:00
Henry Cook
93773a4496 Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks. 
To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).

Closes #18
Closes #20
 2016-03-10 17:14:34 -08:00
Andrew Waterman
36f2e6504c Fix width of NastiROM rows, preventing out-of-range extraction 2016-03-03 16:57:16 -08:00
Henry Cook
7eef3393f1 fix bug resulting in different g_types on tail beats in L2CacheBank.io.inner.grant 2016-03-02 14:11:45 -08:00
Henry Cook
57370bdf49 first and last on HasTileLinkData 2016-03-02 14:11:39 -08:00
Palmer Dabbelt
4acdc67485 Add an assertion in the NastiIOTileLink converter 
This uses an reorder queue but doesn't check to ensure that the data it fetches
from the queue is actually in the queue before using it.  It seems that during
correct operation this never breaks, but I'm trying to get the backup memory
port working again and this assertion fails with it enabled (without the
assertion the core just gets a bogus data beat dies).

Closes #16
 2016-03-01 12:23:32 -08:00