riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao 7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
Howard Mao f78da0b0ea add required cloneType methods in non-blocking L1 2016-08-19 13:44:53 -07:00
Howard Mao 33676e81f8 use isOneOf as much as possible 2016-08-19 09:56:06 -07:00
Howard Mao d34e790ac0 get rid of duplicated code in rocket Util 2016-08-18 18:40:07 -07:00
Howard Mao 7671811ac9 merge uncore.Util into uncore.util 2016-08-18 18:33:46 -07:00
Howard Mao 91a97d6773 add some more comments to describe the new device system 2016-08-18 15:06:55 -07:00
Howard Mao 1b6fa70b5c Add test for external TL clients (bus mastering) 2016-08-18 14:26:03 -07:00
Howard Mao 18982d7351 add default addrMapEntry definition which throws exception 2016-08-18 12:29:41 -07:00
Howard Mao f7c42499bb allow ExtraDevices to have client ports as well as MMIO ports 2016-08-18 12:18:14 -07:00
Howard Mao d771f37e7e rename BusPorts to ExternalClients 2016-08-18 10:54:24 -07:00
Howard Mao 10190197c3 allow coreplex to take in more than 1 bus port 2016-08-18 10:35:25 -07:00
Howard Mao 35fbbfc70d put test harness on the heap in emulator 2016-08-16 14:50:40 -07:00
Howard MaoandAndrew Waterman 38e0967816 strip DMA and RoCC CSRs out of rocket and uncore (#201) 2016-08-15 23:08:55 -07:00
Howard Mao 47a0c880a4 make sure TLId set in Periphery 2016-08-15 13:58:23 -07:00
Howard Mao e939af88aa explicitly set TLId for bus TL ports 2016-08-15 12:46:29 -07:00
Howard Mao 2c39f039b5 make external address map order overrideable 2016-08-15 11:40:28 -07:00
Howard Mao fb476d193c refactor main App for better code re-use 2016-08-11 16:15:23 -07:00
Howard Mao a756856d84 make sure coreplex sources included in make dependencies 2016-08-11 14:27:03 -07:00
Howard Mao e0ae039235 fix config string generation for extra devices 2016-08-11 10:44:32 -07:00
Howard Mao 647dbefd9b split coreplex off into separate package 2016-08-10 18:04:22 -07:00
Howard Mao 163cba6a85 make sure all regressions actually run 2016-08-10 14:52:06 -07:00
Howard Mao 4bfa7ceb6a unit tests in Coreplex instead of Tile 2016-08-10 11:26:14 -07:00
Howard Mao 571d579b86 get unit tests working again 2016-08-10 11:23:07 -07:00
Howard Mao 0ee1ce4366 separate Coreplex and TopLevel parameter traits 2016-08-10 09:49:56 -07:00
Howard Mao f95d319162 don't use secondary external address map; collapse submap instead 2016-08-09 22:29:38 -07:00
Howard Mao 2645f74af2 clean up addrmap flatten function 2016-08-09 22:14:32 -07:00
Howard Mao 33f13d5c49 don't repeat external addr map base 2016-08-09 21:20:54 -07:00
Howard Mao 3ea2f4a6c4 refactor top-level into coreplex and platform 2016-08-09 18:26:52 -07:00
Howard Mao 993da60f2c relax address map alignment requirement 2016-08-09 18:25:32 -07:00
Howard Mao 33d5905c50 don't synthesize vsim verilog in Travis 2016-08-09 18:24:59 -07:00
Howard Mao 405294167f fix TL -> Nasti converter w id 2016-08-09 18:24:23 -07:00
Howard MaoandAndrew Waterman 2a5aeeae24 add sbt pack plugin (#197) 2016-08-08 19:31:03 -07:00
Howard Mao dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Howard Mao 9fa5b228b2 allow extra devices and top-level ports to be added without changing RocketChip.scala 2016-08-04 14:06:14 -07:00
Howard Mao 9c4e57aea5 example Rocc accelerator fixes 2016-08-04 11:17:13 -07:00
Howard Mao 410e3e5366 make sure TraceGen gets correct addresses 2016-08-04 11:08:25 -07:00
Howard Mao 0a85e92652 Allow additional internal MMIO devices to be created without changing BaseConfig 2016-08-04 11:04:52 -07:00
Howard Mao f04aefc95c get rid of deprecated ZynqAdapter 2016-08-02 13:14:20 -07:00
Howard Mao 63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
Howard Mao b7723f1ff8 make unit tests local to the packages being tested 2016-08-01 17:02:00 -07:00
Howard Mao 98eede0505 some refactoring in RocketChip top-level 2016-08-01 17:02:00 -07:00
Howard Mao f34b0b0447 make sure L2 tracker doesn't read data array again if data buffer already filled 2016-07-29 16:47:31 -07:00
Howard Mao 2891eb879a add MergedPutRegression to uncover merged put after release bug in L2 2016-07-29 16:42:28 -07:00
Howard Mao 064020bdd7 make sure Memtest generators write different data to each address 2016-07-29 14:22:46 -07:00
Howard Mao 5a3beca097 add RepeatedGetRegression to uncover L2 merged get miss bug 2016-07-28 19:58:47 -07:00
Howard Mao cb86aaa46b fix trace generator addresses 2016-07-28 17:56:14 -07:00
Howard Mao bd5972503f move groundtest/scripts to top-level scripts/ 2016-07-28 11:36:55 -07:00
Howard Mao 478f494626 Merge remote-tracking branch 'groundtest/master' into mono-repo 2016-07-28 11:28:06 -07:00
Howard Mao a5b88d0bdc Merge remote-tracking branch 'junctions/master' into mono-repo 2016-07-28 11:27:47 -07:00
Howard Mao 373fd427dc Merge remote-tracking branch 'rocket/master' into mono-repo 2016-07-28 11:27:29 -07:00
Howard Mao ce242b8f3f Merge remote-tracking branch 'uncore/master' into mono-repo 2016-07-28 11:23:31 -07:00
Howard Mao aefba04fb3 get rid of submodules in preparation for merging 2016-07-28 11:21:08 -07:00
Howard Mao 6de2a3e3b1 get rid of fpga-zynq submodule 2016-07-28 11:07:47 -07:00
Howard Mao fe51a35fa9 a few more submodule bumps 2016-07-28 09:25:59 -07:00
Howard Mao bf35f980a6 make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement 2016-07-27 18:40:38 -07:00
Howard Mao fbcc7317cf make sure PseudoLRU is given power of 2 ways 2016-07-27 18:39:33 -07:00
Howard Mao 15d1aa9346 make sure TrackerAllocationIO addr_block has correct direction set 2016-07-27 16:47:22 -07:00
Howard Mao 9c89290efc fix LRSC issue (fixes issue #86) 2016-07-26 22:25:04 -07:00
Howard Mao 0bd7ef1278 re-enable SCs inflight with other requests 2016-07-26 22:21:41 -07:00
Howard Mao df07771fa0 add uncached noise generator to TraceGen 2016-07-26 22:21:10 -07:00
Howard Mao dcfcac9530 fix LRSC issue (RocketChip issue #86) 
It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.

This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.

The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
 2016-07-26 18:41:52 -07:00
Howard Mao ecd1af326c fix L2 deadlock bug and add more advanced trace generator 2016-07-26 12:43:08 -07:00
Howard Mao 82bbbf908d Fix L2 Writeback deadlock issue 
The deadlock condition occurs when the acquire tracker attempts to
request a writeback while the writeback unit is still busy and a
voluntary release for the block to be written back is coming in.

The voluntary release cannot be accepted because it conflicts with the
acquire tracker. The acquire tracker can't merge the voluntary release
because it is waiting to send the writeback. The writeback can't
progress because the release it is waiting on is behind the voluntary
release.

The solution to this is to break the atomicity guarantee between the
acquire tracker and the writeback unit. This allows the voluntary
release tracker to take the voluntary release before the writeback unit
accepts the conflicting request. This causes a potential race condition
for the metadata array. The solution to this is to have the writeback
unit re-read the metadata after accepting a request.
 2016-07-26 12:31:08 -07:00
Howard Mao 1063d90993 make sure L1 and L2 agree on coherence policy 2016-07-25 12:20:49 -07:00
Howard Mao 6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Howard Mao 51edd19e85 add U bit to misa register 2016-07-22 14:22:59 -07:00
Howard Mao 75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Howard Mao 9168f35971 clean up the requirements in StatelessBridge 
* No need to check that release ID bits and acquire ID bits the same
 * Check that inner and outer coherence policies match
 2016-07-21 19:41:56 -07:00
Howard Mao 12067a3b8d make sure outer probe and finish lines are disconnected 2016-07-21 15:15:44 -07:00
Howard Mao c38dff0855 add some more warnings about the StatelessBridge 2016-07-21 15:07:10 -07:00
Howard Mao 0a1cd64786 fix number of builtin Acquire types 2016-07-21 13:45:20 -07:00
Howard Mao ffe17cbb2b bump uncore for L2 bugfix 2016-07-21 12:35:38 -07:00
Howard Mao 20df74d138 generate more L1 voluntary releases in TraceGen 2016-07-21 12:33:55 -07:00
Howard Mao 86e31be820 fix lockup from back to back releases with data 2016-07-21 12:06:58 -07:00
Howard Mao 24ef4e6dea make sure to use AND not OR for combining finished signals 2016-07-21 12:05:11 -07:00
Howard Mao d77d0ddc5d rename CacheTest.scala to CacheFillTest.scala 2016-07-20 20:37:45 -07:00
Howard Mao d56362f04c add configuration checks for TraceGen 2016-07-20 10:37:10 -07:00
Howard Mao 959630630a give LCG an inc signal and add object constructors 2016-07-20 10:36:28 -07:00
Howard Mao b013925ab0 make sure ReleaseRegression starts only on io.start 2016-07-19 15:42:45 -07:00
Howard Mao 577c73667b use getSimpleName to dump out test names 2016-07-19 14:42:58 -07:00
Howard Mao 1dac2930eb fix bug in WriteMaskedPutBlockRegression 2016-07-19 14:42:23 -07:00
Howard Mao 19b44ec95b Bug fixes in SimpleHellaCacheIF and L2 agents 
* SimpleHellaCacheIF now properly handles both the non-blocking data
   cache and blocking data cache.
 * SimpleHellaCacheIF maintains ordering of replayed requests
 * L2 VoluntaryReleaseTracker sends voluntary release grant properly
 * Coherence protocols now downgrade for probeCopy
 2016-07-19 09:35:13 -07:00
Howard Mao bc39d52655 changes to multi-transaction timer 2016-07-18 18:26:18 -07:00
Howard Mao 9eeb1112d4 fix Bufferless irel_vs_iacq_conflict signal 2016-07-18 17:38:20 -07:00
Howard Mao e5cccc0526 don't update xact_vol_irel if not a voluntary irel 2016-07-18 17:05:23 -07:00
Howard Mao 2723b2f515 fix issues in SimpleHellaCacheIF and document the changes 2016-07-18 17:02:47 -07:00
Howard Mao 40a146f625 HellaCacheArbiter passes through if n == 1 2016-07-18 17:01:29 -07:00
Howard Mao 39a1ecbf3c switch groundtest to merged master 2016-07-18 09:34:27 -07:00
Howard Mao 359252fdc1 fix a width bug 2016-07-18 09:33:17 -07:00
Howard Mao 6fc4236782 add atomic and prefetch drivers 2016-07-18 09:33:17 -07:00
Howard Mao 2ec736ed67 reorder some code in the Nasti unit tests 2016-07-18 09:33:17 -07:00
Howard Mao 3ea299b062 make unit test debug output more meaningful 2016-07-18 09:33:17 -07:00
Howard Mao def740406c fix a few Driver bugs 2016-07-18 09:33:17 -07:00
Howard Mao 8278a73e83 group unit tests by their tested interface 2016-07-18 09:33:17 -07:00
Howard Mao 9c0fffdd1c start constructing composable tilelink unit test drivers 2016-07-18 09:33:17 -07:00
Howard Mao c92732dcaa rename MemoryTestDriver to NastiDriver 2016-07-18 09:33:16 -07:00
Howard Mao c906e6edde some renaming 2016-07-18 09:33:16 -07:00
Howard Mao 1c2bf6e938 make list of unit tests a a parameter 2016-07-18 09:33:16 -07:00
Howard Mao 69eebaf362 factor out unit tests into separate package 2016-07-18 09:33:16 -07:00
Howard Mao e08ec42bc0 refactor groundtest unittests into separate package 2016-07-16 23:19:55 -07:00