use isOneOf as much as possible
This commit is contained in:
parent
d34e790ac0
commit
33676e81f8
@ -4,6 +4,7 @@ import Chisel._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.agents._
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import uncore.util._
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import cde.{Parameters, Field}
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class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
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@ -13,7 +14,7 @@ class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
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val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val active = state === s_prefetch || state === s_retrieve
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val active = state.isOneOf(s_prefetch, s_retrieve)
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val xact_pending = Reg(init = UInt(0, tlMaxClientXacts))
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val xact_id = PriorityEncoder(~xact_pending)
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@ -4,6 +4,7 @@ import Chisel._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.agents._
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import uncore.util._
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import junctions.{ParameterizedBundle, HasAddrMapParameters, Timer}
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import rocket.HellaCacheIO
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import cde.{Parameters, Field}
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@ -159,7 +160,7 @@ class NoAllocPutHitRegression(implicit p: Parameters) extends Regression()(p) {
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client_xact_id = UInt(2),
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addr_block = addr_block)
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io.mem.acquire.valid := (state === s_prefetch) || (state === s_get) || (state === s_put)
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io.mem.acquire.valid := state.isOneOf(s_prefetch, s_get, s_put)
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io.mem.acquire.bits := MuxCase(get_acq, Seq(
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(state === s_prefetch) -> prefetch_acq,
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(state === s_put) -> put_acq))
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@ -235,11 +236,11 @@ class MixedAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
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addr_block = test_block(get_acq_id),
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addr_beat = test_beat(get_acq_id))
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io.mem.acquire.valid := (state === s_pf_send) || (state === s_put_send) || (state === s_get_send)
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io.mem.acquire.valid := state.isOneOf(s_pf_send, s_put_send, s_get_send)
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io.mem.acquire.bits := MuxLookup(state, pf_acquire, Seq(
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s_put_send -> put_acquire,
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s_get_send -> get_acquire))
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io.mem.grant.ready := (state === s_pf_wait) || (state === s_put_wait) || (state === s_get_wait)
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io.mem.grant.ready := state.isOneOf(s_pf_wait, s_put_wait, s_get_wait)
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when (state === s_idle && io.start) { state := s_pf_send }
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when (state === s_pf_send && io.mem.acquire.ready) { state := s_pf_wait }
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@ -321,9 +322,9 @@ class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()
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client_xact_id = UInt(0),
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addr_block = UInt(memStartBlock + 6) + stage)
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io.mem.acquire.valid := (state === s_put_send || state === s_get_send)
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io.mem.acquire.valid := state.isOneOf(s_put_send, s_get_send)
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io.mem.acquire.bits := Mux(state === s_get_send, get_acq, put_acq)
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io.mem.grant.ready := (state === s_put_ack || state === s_get_ack)
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io.mem.grant.ready := state.isOneOf(s_put_ack, s_get_ack)
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val (get_cnt, get_done) = Counter(
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io.mem.grant.fire() && gnt.hasData(), tlDataBeats)
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@ -491,7 +492,7 @@ class ReleaseRegression(implicit p: Parameters) extends Regression()(p) {
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val s_idle :: s_write :: s_read :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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io.cache.req.valid := sending && (state === s_write || state === s_read)
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io.cache.req.valid := sending && state.isOneOf(s_write, s_read)
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io.cache.req.bits.addr := Cat(addr_blocks(req_idx), UInt(0, blockOffset))
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io.cache.req.bits.typ := UInt(log2Ceil(64 / 8))
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io.cache.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
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@ -544,7 +545,7 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p
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val (ack_cnt, all_acked) = Counter(io.mem.grant.fire(), 2)
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io.mem.acquire.valid := (state === s_put) || (state === s_putblock)
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io.mem.acquire.valid := state.isOneOf(s_put, s_putblock)
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io.mem.acquire.bits := Mux(state === s_put, put_acquire, put_block_acquire)
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io.mem.grant.ready := (state === s_wait)
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@ -349,7 +349,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R && priv_sufficient
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val wen = cpu_wen && !read_only
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val wdata = (Mux((io.rw.cmd === CSR.S || io.rw.cmd === CSR.C), io.rw.rdata, UInt(0)) |
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val wdata = (Mux(io.rw.cmd.isOneOf(CSR.S, CSR.C), io.rw.rdata, UInt(0)) |
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Mux(io.rw.cmd =/= CSR.C, io.rw.wdata, UInt(0))) &
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~Mux(io.rw.cmd === CSR.C, io.rw.wdata, UInt(0))
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@ -88,7 +88,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val release_state = Reg(init=s_ready)
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val pstore1_valid = Wire(Bool())
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val pstore2_valid = Reg(Bool())
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val inWriteback = release_state === s_voluntary_writeback || release_state === s_probe_rep_dirty
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val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty)
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val releaseWay = Wire(UInt())
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io.cpu.req.ready := (release_state === s_ready) && !grant_wait && !s1_nack
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@ -345,14 +345,14 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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}
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}
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when (releaseDone) { release_state := s_ready }
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when (release_state === s_probe_rep_miss || release_state === s_probe_rep_clean) {
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when (release_state.isOneOf(s_probe_rep_miss, s_probe_rep_clean)) {
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io.mem.release.valid := true
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}
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when (release_state === s_probe_rep_clean || release_state === s_probe_rep_dirty) {
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when (release_state.isOneOf(s_probe_rep_clean, s_probe_rep_dirty)) {
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io.mem.release.bits := probeResponseMessage
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when (releaseDone) { release_state := s_probe_write_meta }
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}
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when (release_state === s_voluntary_writeback || release_state === s_voluntary_write_meta) {
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when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta)) {
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io.mem.release.bits := voluntaryReleaseMessage
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newCoh := voluntaryNewCoh
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releaseWay := s2_victim_way
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@ -371,7 +371,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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dataArb.io.in(2).bits.addr := Cat(io.mem.release.bits.addr_block, releaseDataBeat(log2Up(refillCycles)-1,0)) << rowOffBits
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dataArb.io.in(2).bits.way_en := ~UInt(0, nWays)
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metaWriteArb.io.in(2).valid := (release_state === s_voluntary_write_meta || release_state === s_probe_write_meta)
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metaWriteArb.io.in(2).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta)
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metaWriteArb.io.in(2).bits.way_en := releaseWay
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metaWriteArb.io.in(2).bits.idx := io.mem.release.bits.full_addr()(idxMSB, idxLSB)
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metaWriteArb.io.in(2).bits.data.coh := newCoh
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@ -282,12 +282,6 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(UInt(), 9)
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val state = Reg(init=s_invalid)
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def stateIsOneOf(check_states: Seq[UInt]): Bool =
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check_states.map(state === _).reduce(_ || _)
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def stateIsOneOf(st1: UInt, st2: UInt*): Bool =
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stateIsOneOf(st1 +: st2)
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val new_coh_state = Reg(init=ClientMetadata.onReset)
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val req = Reg(new MSHRReqInternal())
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val req_idx = req.addr(untagBits-1,blockOffBits)
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@ -306,14 +300,14 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val (refill_cnt, refill_count_done) = Counter(io.mem_grant.valid && gnt_multi_data, refillCycles)
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val refill_done = io.mem_grant.valid && (!gnt_multi_data || refill_count_done)
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val sec_rdy = idx_match &&
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(stateIsOneOf(states_before_refill) ||
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(stateIsOneOf(s_refill_req, s_refill_resp) &&
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(state.isOneOf(states_before_refill) ||
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(state.isOneOf(s_refill_req, s_refill_resp) &&
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!cmd_requires_second_acquire && !refill_done))
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val rpq = Module(new Queue(new ReplayInternal, p(ReplayQueueDepth)))
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd)
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rpq.io.enq.bits := io.req_bits
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rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid
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rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) || state === s_invalid
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val coh_on_grant = req.old_meta.coh.onGrant(
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incoming = io.mem_grant.bits,
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@ -373,7 +367,7 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val fq = Module(new FinishQueue(1))
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val g = io.mem_grant.bits
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val can_finish = state === s_invalid || state === s_refill_req
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val can_finish = state.isOneOf(s_invalid, s_refill_req)
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fq.io.enq.valid := io.mem_grant.valid && g.requiresAck() && refill_done
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fq.io.enq.bits := g.makeFinish()
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io.mem_finish.valid := fq.io.deq.valid && can_finish
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@ -390,9 +384,9 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val meta_hazard = Reg(init=UInt(0,2))
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when (meta_hazard =/= UInt(0)) { meta_hazard := meta_hazard + 1 }
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when (io.meta_write.fire()) { meta_hazard := 1 }
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io.probe_rdy := !idx_match || (!stateIsOneOf(states_before_refill) && meta_hazard === 0)
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io.probe_rdy := !idx_match || (!state.isOneOf(states_before_refill) && meta_hazard === 0)
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io.meta_write.valid := state === s_meta_write_req || state === s_meta_clear
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io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear)
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io.meta_write.bits.idx := req_idx
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io.meta_write.bits.data.coh := Mux(state === s_meta_clear,
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req.old_meta.coh.onCacheControl(M_FLUSH),
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@ -130,7 +130,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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pte_wdata.a := true
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pte_wdata.d := r_req.store
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io.mem.req.valid := state === s_req || state === s_set_dirty
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io.mem.req.valid := state.isOneOf(s_req, s_set_dirty)
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io.mem.req.bits.phys := Bool(true)
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io.mem.req.bits.cmd := Mux(state === s_set_dirty, M_XA_OR, M_XRD)
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io.mem.req.bits.typ := log2Ceil(xLen/8)
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@ -74,7 +74,7 @@ class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
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(0 until max_size).map(sz => (UInt(sz) -> UInt((1 << (1 << sz)) - 1))))
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val wmask = (wmask_lut << waddr(max_size - 1, 0))(hastiDataBytes - 1, 0)
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val is_trans = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
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val is_trans = io.hsel && io.htrans.isOneOf(HTRANS_NONSEQ, HTRANS_SEQ)
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val raddr = io.haddr >> UInt(max_size)
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val ren = is_trans && !io.hwrite
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val bypass = Reg(init = Bool(false))
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@ -4,6 +4,7 @@ package uncore.devices
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import Chisel._
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import uncore.tilelink._
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import uncore.util._
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import junctions._
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import cde.{Parameters, Config, Field}
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@ -901,7 +902,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
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when (sbAddr(11, 8) === UInt(4)) { //0x400-0x4FF Debug RAM
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sbRdData := sbRamRdData
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sbRamRdEn := sbRdEn
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}.elsewhen (sbAddr(11,8) === UInt(8) || sbAddr(11,8) === UInt(9)){ //0x800-0x9FF Debug ROM
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}.elsewhen (sbAddr(11,8).isOneOf(UInt(8), UInt(9))){ //0x800-0x9FF Debug ROM
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if (cfg.hasDebugRom) {
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sbRdData := sbRomRdData
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} else {
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@ -4,6 +4,7 @@ import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.util._
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import cde.Parameters
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abstract class Driver(implicit p: Parameters) extends TLModule()(p) {
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@ -167,7 +168,7 @@ class PutSweepDriver(val n: Int)(implicit p: Parameters) extends Driver()(p) {
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val put_data = Fill(dataRep, put_cnt)(tlDataBits - 1, 0)
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val get_data = Fill(dataRep, get_cnt)(tlDataBits - 1, 0)
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io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
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io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
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io.mem.acquire.bits := Mux(state === s_put_req,
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Put(
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client_xact_id = UInt(0),
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@ -178,7 +179,7 @@ class PutSweepDriver(val n: Int)(implicit p: Parameters) extends Driver()(p) {
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client_xact_id = UInt(0),
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addr_block = get_block,
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addr_beat = get_beat))
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io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
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io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
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when (state === s_idle && io.start) { state := s_put_req }
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when (state === s_put_req && io.mem.acquire.ready) { state := s_put_resp }
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@ -239,7 +240,7 @@ class PutMaskDriver(minBytes: Int = 1)(implicit p: Parameters) extends Driver()(
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}
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io.finished := (state === s_done)
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io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
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io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
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io.mem.acquire.bits := Mux(state === s_put_req,
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Put(
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client_xact_id = UInt(0),
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@ -251,7 +252,7 @@ class PutMaskDriver(minBytes: Int = 1)(implicit p: Parameters) extends Driver()(
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client_xact_id = UInt(0),
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addr_block = UInt(0),
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addr_beat = UInt(0)))
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io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
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io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
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assert(!io.mem.grant.valid || state =/= s_get_resp ||
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io.mem.grant.bits.data === expected,
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@ -295,9 +296,9 @@ class PutBlockSweepDriver(val n: Int)(implicit p: Parameters)
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addr_block = get_cnt)
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io.finished := (state === s_done)
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io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
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io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
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io.mem.acquire.bits := Mux(state === s_put_req, put_acquire, get_acquire)
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io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
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io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
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assert(!io.mem.grant.valid || state =/= s_get_resp ||
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io.mem.grant.bits.data === get_data,
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