make sure TraceGen gets correct addresses
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@ -210,8 +210,9 @@ class WithTraceGen extends Config(
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val nWays = 1
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val blockOffset = site(CacheBlockOffsetBits)
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val baseAddr = site(GlobalAddrMap)("mem").start
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val nBeats = site(MIFDataBeats)
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List.tabulate(4 * nWays) { i =>
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Seq.tabulate(2) { j => (i * nSets + j * 8) << blockOffset }
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Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
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}.flatten.map(addr => baseAddr + BigInt(addr))
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}
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case UseAtomics => true
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