riscv/rocket-chip
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allow coreplex to take in more than 1 bus port

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This commit is contained in:
Howard Mao 2016-08-18 10:34:01 -07:00
parent de316643d1
commit 10190197c3
7 changed files with 19 additions and 18 deletions
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2
coreplex/src/main/scala/Configs.scala
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@ -160,7 +160,7 @@ class BaseCoreplexConfig extends Config (
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = (if (site(ExportBusPort)) 1 else 0) + site(NUncachedTileLinkPorts),
nCachelessClients = site(NBusPorts) + site(NUncachedTileLinkPorts),
maxClientXacts = max_int(
// L1 cache
site(NMSHRs) + 1 /* IOMSHR */,

16
coreplex/src/main/scala/Coreplex.scala
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@ -36,8 +36,8 @@ case object RTCPeriod extends Field[Int]
case object BootROMFile extends Field[String]
/** Export an external MMIO slave port */
case object ExportMMIOPort extends Field[Boolean]
/** Expose an additional bus master port */
case object ExportBusPort extends Field[Boolean]
/** Expose additional bus master ports */
case object NBusPorts extends Field[Int]
/** Extra top-level ports exported from the coreplex */
case object ExtraCoreplexPorts extends Field[Parameters => Bundle]
@ -53,7 +53,7 @@ trait HasCoreplexParameters {
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
lazy val exportBus = p(ExportBusPort)
lazy val nBusPorts = p(NBusPorts)
lazy val exportMMIO = p(ExportMMIOPort)
}
@ -69,7 +69,7 @@ class Uncore(implicit val p: Parameters) extends Module
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val prci = Vec(nTiles, new PRCITileIO).asOutput
val bus = if (exportBus) Some(new ClientUncachedTileLinkIO()(innerParams).flip) else None
val bus = Vec(nBusPorts, new ClientUncachedTileLinkIO()(innerParams)).flip
val mmio = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val debug = new DebugBusIO()(p).flip
@ -81,7 +81,7 @@ class Uncore(implicit val p: Parameters) extends Module
outmemsys.io.incoherent foreach (_ := false)
outmemsys.io.tiles_uncached <> io.tiles_uncached
outmemsys.io.tiles_cached <> io.tiles_cached
if (exportBus) { outmemsys.io.bus.get <> io.bus.get }
outmemsys.io.bus <> io.bus
io.mem <> outmemsys.io.mem
buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"}))
@ -147,7 +147,7 @@ abstract class OuterMemorySystem(implicit val p: Parameters)
val io = new Bundle {
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val bus = if (exportBus) Some(new ClientUncachedTileLinkIO()(innerParams).flip) else None
val bus = Vec(nBusPorts, new ClientUncachedTileLinkIO()(innerParams)).flip
val incoherent = Vec(nCachedTilePorts, Bool()).asInput
val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
@ -232,7 +232,7 @@ abstract class Coreplex(implicit val p: Parameters) extends Module
with HasCoreplexParameters {
class CoreplexIO(implicit val p: Parameters) extends Bundle {
val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
val bus = if (p(ExportBusPort)) Some(new ClientUncachedTileLinkIO()(innerParams).flip) else None
val bus = Vec(nBusPorts, new ClientUncachedTileLinkIO()(innerParams)).flip
val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val debug = new DebugBusIO()(p).flip
@ -273,7 +273,7 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
uncore.io.interrupts <> io.interrupts
uncore.io.debug <> io.debug
if (exportBus) { uncore.io.bus.get <> io.bus.get }
uncore.io.bus <> io.bus
if (exportMMIO) { io.mmio.get <> uncore.io.mmio.get }
io.mem <> uncore.io.mem
}

2
coreplex/src/main/scala/DirectGroundTest.scala
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@ -14,7 +14,7 @@ class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topPara
io.debug.resp.valid := Bool(false)
require(!exportMMIO)
require(!exportBus)
require(nBusPorts == 0)
require(nMemChannels == 1)
require(nTiles == 1)

2
coreplex/src/main/scala/UnitTest.scala
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@ -8,7 +8,7 @@ import cde.Parameters
class UnitTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
require(!exportMMIO)
require(!exportBus)
require(nBusPorts == 0)
require(nMemChannels == 0)
io.debug.req.ready := Bool(false)

2
firrtl

@ -1 +1 @@
Subproject commit 197760a962633d0e6140bcff16b96cc3d6b4e776
Subproject commit 5db4abebb7ceb5939a9efca158d78e3dc0e32c44

2
src/main/scala/Configs.scala
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@ -132,7 +132,7 @@ class BasePlatformConfig extends Config (
case ExportMMIOPort => (site(ExtraDevices).size + site(ExtMMIOPorts).size) > 0
case AsyncBusChannels => false
case NExtBusAXIChannels => 0
case ExportBusPort => site(NExtBusAXIChannels) > 0
case NBusPorts => if (site(NExtBusAXIChannels) > 1) 1 else 0
case ConnectExtraPorts =>
(out: Bundle, in: Bundle, p: Parameters) => out <> in

11
src/main/scala/RocketChip.scala
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@ -57,7 +57,6 @@ trait HasTopLevelParameters {
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
lazy val exportBus = p(ExportBusPort)
lazy val exportMMIO = p(ExportMMIOPort)
}
@ -135,7 +134,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
if (exportMMIO) { periphery.io.mmio_in.get <> coreplex.io.mmio.get }
periphery.io.mem_in <> coreplex.io.mem
if (exportBus) { coreplex.io.bus.get <> periphery.io.bus_out.get }
coreplex.io.bus <> periphery.io.bus_out
coreplex.io.debug <>
(if (p(AsyncDebugBus))
@ -179,7 +178,7 @@ class Periphery(implicit val p: Parameters) extends Module
with HasTopLevelParameters {
val io = new Bundle {
val mem_in = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)).flip
val bus_out = if (exportBus) Some(new ClientUncachedTileLinkIO()(innerParams)) else None
val bus_out = Vec(p(NBusPorts), new ClientUncachedTileLinkIO()(innerParams))
val mmio_in = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams).flip) else None
val mem_axi = Vec(nMemAXIChannels, new NastiIO)
val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
@ -191,12 +190,14 @@ class Periphery(implicit val p: Parameters) extends Module
val extra = p(ExtraTopPorts)(p)
}
io.bus_out.map { tl_out =>
require(io.bus_out.size <= 1)
if (io.bus_out.size > 0) {
val conv = Module(new TileLinkIONastiIOConverter)
val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
arb.io.master <> io.bus_axi
conv.io.nasti <> conv.io.tl
tl_out <> conv.io.tl
io.bus_out.head <> conv.io.tl
}
def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {