refactor top-level into coreplex and platform
This commit is contained in:
Howard Mao
@@ -34,15 +34,18 @@ class BaseConfig extends Config (
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
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entries ++= site(ExtraDevices).map(_.addrMapEntry)
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new AddrMap(entries)
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}
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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val memSize = 0x10000000L
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val io = new AddrMap(AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries)
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val intern = AddrMapEntry("int", internalIOAddrMap)
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val extern = AddrMapEntry("ext", MemRange(0x50000000L, 0x30000000L, MemAttr(AddrMapProt.RWX)))
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val ioMap = if (site(ExportMMIOPort)) AddrMap(intern, extern) else AddrMap(intern)
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val addrMap = AddrMap(
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AddrMapEntry("io", io),
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AddrMapEntry("io", ioMap),
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AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
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Dump("MEM_BASE", addrMap("mem").start)
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@@ -51,6 +54,7 @@ class BaseConfig extends Config (
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}
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def makeConfigString() = {
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val addrMap = globalAddrMap
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val extAddrMap = site(ExtAddrMap)
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val plicAddr = addrMap("io:int:plic").start
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val prciAddr = addrMap("io:int:prci").start
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val plicInfo = site(PLICKey)
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@@ -97,7 +101,7 @@ class BaseConfig extends Config (
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}
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for (device <- site(ExtraDevices)) {
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val deviceName = device.addrMapEntry.name
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val deviceRegion = addrMap("io:int:" + deviceName)
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val deviceRegion = extAddrMap(deviceName)
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res.append(device.makeConfigString(deviceRegion))
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}
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res append "};\n"
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@@ -188,6 +192,7 @@ class BaseConfig extends Config (
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}
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}
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case BuildRoCC => Nil
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case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
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@@ -231,17 +236,18 @@ class BaseConfig extends Config (
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case AsyncMMIOChannels => false
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case ExtraDevices => Nil
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case ExtraTopPorts => (p: Parameters) => new Bundle
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case ExtMMIOPorts => AddrMap()
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/*
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AddrMap(
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AddrMapEntry("cfg", MemRange(0x50000000L, 0x04000000L, MemAttr(AddrMapProt.RW))),
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AddrMapEntry("ext", MemRange(0x60000000L, 0x20000000L, MemAttr(AddrMapProt.RWX))))
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*/
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case ExtMMIOPorts => Nil
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case ExtAddrMap => new AddrMap(
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site(ExtraDevices).map(_.addrMapEntry) ++
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site(ExtMMIOPorts),
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start = BigInt("50000000", 16))
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case ExportMMIOPort => (site(ExtraDevices).size + site(ExtMMIOPorts).size) > 0
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case ExportBusPort => site(NExtBusAXIChannels) > 0
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
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case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
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case FDivSqrt => true
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255
src/main/scala/Coreplex.scala
Normal file
255
src/main/scala/Coreplex.scala
Normal file
@@ -0,0 +1,255 @@
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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import java.nio.{ByteBuffer,ByteOrder}
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import java.nio.file.{Files, Paths}
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** A string describing on-chip devices, readable by target software */
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case object ConfigString extends Field[Array[Byte]]
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/** Number of external interrupt sources */
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case object NExtInterrupts extends Field[Int]
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/** Interrupt controller configuration */
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case object PLICKey extends Field[PLICConfig]
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/** Number of clock cycles per RTC tick */
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case object RTCPeriod extends Field[Int]
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/** The file to read the BootROM contents from */
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case object BootROMFile extends Field[String]
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/** Export an external MMIO slave port */
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case object ExportMMIOPort extends Field[Boolean]
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/** Expose an additional bus master port */
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case object ExportBusPort extends Field[Boolean]
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/** Function for building Coreplex */
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case object BuildCoreplex extends Field[Parameters => Coreplex]
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/** Wrapper around everything that isn't a Tile.
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*
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* Usually this is clocked and/or place-and-routed separately from the Tiles.
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*/
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class Uncore(implicit val p: Parameters) extends Module
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with HasTopLevelParameters {
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val io = new Bundle {
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val prci = Vec(nTiles, new PRCITileIO).asOutput
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val bus = if (exportBus) Some(new ClientUncachedTileLinkIO().flip) else None
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val mmio = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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}
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val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0)
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Module(new OuterMemorySystem) // NoC, LLC and SerDes
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else Module(new DummyOuterMemorySystem)
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outmemsys.io.incoherent foreach (_ := false)
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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if (exportBus) { outmemsys.io.bus.get <> io.bus.get }
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io.mem <> outmemsys.io.mem
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buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"}))
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def makeBootROM()(implicit p: Parameters) = {
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val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
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val rom = ByteBuffer.wrap(romdata)
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rom.order(ByteOrder.LITTLE_ENDIAN)
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// for now, have the reset vector jump straight to memory
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val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector)
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require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
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val configStringAddr = p(ResetVector).toInt + rom.capacity
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require(rom.getInt(12) == 0,
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"Config string address position should not be occupied by code")
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rom.putInt(12, configStringAddr)
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rom.array() ++ p(ConfigString).toSeq
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}
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def buildMMIONetwork(implicit p: Parameters) = {
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val ioAddrMap = p(GlobalAddrMap).subMap("io")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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mmioNetwork.io.in.head <> outmemsys.io.mmio
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val plic = Module(new PLIC(p(PLICKey)))
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plic.io.tl <> mmioNetwork.port("int:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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plic.io.devices(i) <> gateway.io.plic
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}
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val debugModule = Module(new DebugModule)
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debugModule.io.tl <> mmioNetwork.port("int:debug")
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debugModule.io.db <> io.debug
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val prci = Module(new PRCI)
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prci.io.tl <> mmioNetwork.port("int:prci")
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io.prci := prci.io.tiles
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prci.io.rtcTick := Counter(p(RTCPeriod)).inc() // placeholder for real RTC
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for (i <- 0 until nTiles) {
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prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
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if (p(UseVM))
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prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
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prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
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io.prci(i).reset := reset
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}
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val bootROM = Module(new ROMSlave(makeBootROM()))
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bootROM.io <> mmioNetwork.port("int:bootrom")
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io.mmio.map { ext => ext <> mmioNetwork.port("ext") }
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}
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}
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abstract class AbstractOuterMemorySystem(implicit val p: Parameters)
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extends Module with HasTopLevelParameters {
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val io = new Bundle {
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val bus = if (exportBus) Some(new ClientUncachedTileLinkIO().flip) else None
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val incoherent = Vec(nCachedTilePorts, Bool()).asInput
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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}
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/** Use in place of OuterMemorySystem if there are no clients to connect. */
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class DummyOuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySystem()(p) {
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require(nCachedTilePorts + nUncachedTilePorts == 0)
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require(io.bus.isEmpty)
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io.mem.foreach { tl =>
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tl.acquire.valid := Bool(false)
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tl.grant.ready := Bool(false)
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}
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io.mmio.acquire.valid := Bool(false)
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io.mmio.grant.ready := Bool(false)
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}
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/** The whole outer memory hierarchy, including a NoC, some kind of coherence
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* manager agent, and a converter from TileLink to MemIO.
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*/
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class OuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySystem()(p) {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = {
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val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory,
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if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
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UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(1,1,2,2,0)
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.foreach { _.incoherent := io.incoherent }
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val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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case TLId => "L1toL2"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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io.mmio <> mmioManager.io.outer
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// Wire the tiles to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> io.tiles_cached
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l1tol2net.io.clients_uncached <> io.tiles_uncached ++ io.bus
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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// TODO: the code to print this stuff should live somewhere else
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println("Generated Address Map")
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for ((name, region) <- p(GlobalAddrMap).flatten) {
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println(f"\t$name%s ${region.start}%x - ${region.start + region.size - 1}%x")
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}
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println("Generated Configuration String")
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println(new String(p(ConfigString)))
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostParams))
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
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TileLinkWidthAdapter(icPort, unwrap.io.out)
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}
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io.mem <> mem_ic.io.out
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}
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abstract class Coreplex(implicit val p: Parameters) extends Module
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with HasTopLevelParameters {
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val io = new Bundle {
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val bus = if (p(ExportBusPort)) Some(new ClientUncachedTileLinkIO().flip) else None
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val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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}
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}
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class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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// Build an Uncore and a set of Tiles
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val tileResets = Wire(Vec(nTiles, Bool()))
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val tileList = p(BuildTiles).zip(tileResets).map {
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case (tile, rst) => tile(rst, p)
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}
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val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
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val innerTLParams = p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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case NCachedTileLinkPorts => nCachedPorts
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case NUncachedTileLinkPorts => nUncachedPorts
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})
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val uncore = Module(new Uncore()(innerTLParams))
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(uncore.io.prci, tileResets, tileList).zipped.foreach {
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case (prci, rst, tile) =>
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rst := prci.reset
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tile.io.prci <> prci
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}
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
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uncore.io.interrupts <> io.interrupts
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uncore.io.debug <> io.debug
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if (exportBus) { uncore.io.bus.get <> io.bus.get }
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if (exportMMIO) { io.mmio.get <> uncore.io.mmio.get }
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io.mem <> uncore.io.mem
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}
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@@ -6,15 +6,10 @@ import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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import java.nio.{ByteBuffer,ByteOrder}
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import java.nio.file.{Files, Paths}
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/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
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@@ -27,38 +22,25 @@ object BusType {
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val busTypes = Seq(AXI, AHB, TL)
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}
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/** Number of memory channels */
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case object AsyncMemChannels extends Field[Boolean]
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case object NMemoryChannels extends Field[Int]
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/** Memory channel controls */
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case object TMemoryChannels extends Field[BusType.EnumVal]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Number of outstanding memory requests */
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case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Number of exteral MMIO ports */
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case object AsyncMMIOChannels extends Field[Boolean]
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case object ExtMMIOPorts extends Field[AddrMap]
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/** External MMIO controls */
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case object NExtMMIOAXIChannels extends Field[Int]
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case object NExtMMIOAHBChannels extends Field[Int]
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case object NExtMMIOTLChannels extends Field[Int]
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case object AsyncBusChannels extends Field[Boolean]
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/** External Bus controls */
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case object NExtBusAXIChannels extends Field[Int]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** A string describing on-chip devices, readable by target software */
|
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case object ConfigString extends Field[Array[Byte]]
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/** Number of external interrupt sources */
|
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case object NExtInterrupts extends Field[Int]
|
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/** Interrupt controller configuration */
|
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case object PLICKey extends Field[PLICConfig]
|
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/** Number of clock cycles per RTC tick */
|
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case object RTCPeriod extends Field[Int]
|
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/** Async configurations */
|
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case object AsyncBusChannels extends Field[Boolean]
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case object AsyncDebugBus extends Field[Boolean]
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case object BootROMFile extends Field[String]
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case object AsyncMemChannels extends Field[Boolean]
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case object AsyncMMIOChannels extends Field[Boolean]
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|
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/** External address map settings */
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case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
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case object ExtAddrMap extends Field[AddrMap]
|
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||||
/** Utility trait for quick access to some relevant parameters */
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trait HasTopLevelParameters {
|
||||
@@ -81,6 +63,8 @@ trait HasTopLevelParameters {
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lazy val xLen = p(XLen)
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||||
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
|
||||
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
|
||||
lazy val exportBus = p(ExportBusPort)
|
||||
lazy val exportMMIO = p(ExportMMIOPort)
|
||||
}
|
||||
|
||||
class MemBackupCtrlIO extends Bundle {
|
||||
@@ -148,34 +132,14 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
|
||||
implicit val p = topParams
|
||||
val io = new TopIO
|
||||
|
||||
// Build an Uncore and a set of Tiles
|
||||
val tileResets = Wire(Vec(nTiles, Bool()))
|
||||
val tileList = p(BuildTiles).zip(tileResets).map {
|
||||
case (tile, rst) => tile(rst, p)
|
||||
}
|
||||
val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
|
||||
val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
|
||||
val coreplex = p(BuildCoreplex)(p)
|
||||
val periphery = Module(new Periphery)
|
||||
|
||||
val innerTLParams = p.alterPartial({
|
||||
case HastiId => "TL"
|
||||
case TLId => "L1toL2"
|
||||
case NCachedTileLinkPorts => nCachedPorts
|
||||
case NUncachedTileLinkPorts => nUncachedPorts
|
||||
})
|
||||
if (exportMMIO) { periphery.io.mmio_in.get <> coreplex.io.mmio.get }
|
||||
periphery.io.mem_in <> coreplex.io.mem
|
||||
if (exportBus) { coreplex.io.bus.get <> periphery.io.bus_out.get }
|
||||
|
||||
val uncore = Module(new Uncore()(innerTLParams))
|
||||
|
||||
(uncore.io.prci, tileResets, tileList).zipped.foreach {
|
||||
case (prci, rst, tile) =>
|
||||
rst := prci.reset
|
||||
tile.io.prci <> prci
|
||||
}
|
||||
|
||||
// Connect the uncore to the tile memory ports, HostIO and MemIO
|
||||
uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
|
||||
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
|
||||
uncore.io.interrupts <> io.interrupts
|
||||
uncore.io.debugBus <>
|
||||
coreplex.io.debug <>
|
||||
(if (p(AsyncDebugBus))
|
||||
AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug)
|
||||
else io.debug)
|
||||
@@ -192,62 +156,49 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
|
||||
|
||||
io.mmio_axi <>
|
||||
(if (p(AsyncMMIOChannels))
|
||||
asyncAxiTo(io.mmio_clk.get, io.mmio_rst.get, uncore.io.mmio_axi)
|
||||
else uncore.io.mmio_axi)
|
||||
io.mmio_ahb <> uncore.io.mmio_ahb
|
||||
io.mmio_tl <> uncore.io.mmio_tl
|
||||
asyncAxiTo(io.mmio_clk.get, io.mmio_rst.get, periphery.io.mmio_axi)
|
||||
else periphery.io.mmio_axi)
|
||||
io.mmio_ahb <> periphery.io.mmio_ahb
|
||||
io.mmio_tl <> periphery.io.mmio_tl
|
||||
|
||||
io.mem_axi <>
|
||||
(if (p(AsyncMemChannels))
|
||||
asyncAxiTo(io.mem_clk.get, io.mem_rst.get, uncore.io.mem_axi)
|
||||
else uncore.io.mem_axi)
|
||||
io.mem_ahb <> uncore.io.mem_ahb
|
||||
io.mem_tl <> uncore.io.mem_tl
|
||||
asyncAxiTo(io.mem_clk.get, io.mem_rst.get, periphery.io.mem_axi)
|
||||
else periphery.io.mem_axi)
|
||||
io.mem_ahb <> periphery.io.mem_ahb
|
||||
io.mem_tl <> periphery.io.mem_tl
|
||||
|
||||
uncore.io.bus_axi <>
|
||||
periphery.io.bus_axi <>
|
||||
(if (p(AsyncBusChannels))
|
||||
asyncAxiFrom(io.bus_clk.get, io.bus_rst.get, io.bus_axi)
|
||||
else io.bus_axi)
|
||||
|
||||
io.extra <> uncore.io.extra
|
||||
io.extra <> periphery.io.extra
|
||||
}
|
||||
|
||||
/** Wrapper around everything that isn't a Tile.
|
||||
*
|
||||
* Usually this is clocked and/or place-and-routed separately from the Tiles.
|
||||
*/
|
||||
class Uncore(implicit val p: Parameters) extends Module
|
||||
class Periphery(implicit val p: Parameters) extends Module
|
||||
with HasTopLevelParameters {
|
||||
|
||||
val io = new Bundle {
|
||||
val mem_in = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)).flip
|
||||
val bus_out = if (exportBus) Some(new ClientUncachedTileLinkIO) else None
|
||||
val mmio_in = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams).flip) else None
|
||||
val mem_axi = Vec(nMemAXIChannels, new NastiIO)
|
||||
val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
|
||||
val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
|
||||
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
|
||||
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
|
||||
val prci = Vec(nTiles, new PRCITileIO).asOutput
|
||||
val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
|
||||
val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
|
||||
val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
|
||||
val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
|
||||
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
|
||||
val debugBus = new DebugBusIO()(p).flip
|
||||
val extra = p(ExtraTopPorts)(p)
|
||||
}
|
||||
|
||||
val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0)
|
||||
Module(new OuterMemorySystem) // NoC, LLC and SerDes
|
||||
else Module(new DummyOuterMemorySystem)
|
||||
outmemsys.io.incoherent foreach (_ := false)
|
||||
outmemsys.io.tiles_uncached <> io.tiles_uncached
|
||||
outmemsys.io.tiles_cached <> io.tiles_cached
|
||||
|
||||
buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"}))
|
||||
|
||||
io.mem_axi <> outmemsys.io.mem_axi
|
||||
io.mem_ahb <> outmemsys.io.mem_ahb
|
||||
io.mem_tl <> outmemsys.io.mem_tl
|
||||
outmemsys.io.bus_axi <> io.bus_axi
|
||||
io.bus_out.map { tl_out =>
|
||||
val conv = Module(new TileLinkIONastiIOConverter)
|
||||
val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
|
||||
arb.io.master <> io.bus_axi
|
||||
conv.io.nasti <> conv.io.tl
|
||||
tl_out <> conv.io.tl
|
||||
}
|
||||
|
||||
def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {
|
||||
val mmio_axi_start = 0
|
||||
@@ -273,189 +224,41 @@ class Uncore(implicit val p: Parameters) extends Module
|
||||
}
|
||||
}
|
||||
|
||||
def makeBootROM()(implicit p: Parameters) = {
|
||||
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
|
||||
val rom = ByteBuffer.wrap(romdata)
|
||||
|
||||
rom.order(ByteOrder.LITTLE_ENDIAN)
|
||||
|
||||
// for now, have the reset vector jump straight to memory
|
||||
val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector)
|
||||
require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
|
||||
val configStringAddr = p(ResetVector).toInt + rom.capacity
|
||||
|
||||
require(rom.getInt(12) == 0,
|
||||
"Config string address position should not be occupied by code")
|
||||
rom.putInt(12, configStringAddr)
|
||||
rom.array() ++ p(ConfigString).toSeq
|
||||
}
|
||||
|
||||
def buildMMIONetwork(implicit p: Parameters) = {
|
||||
val ioAddrMap = p(GlobalAddrMap).subMap("io")
|
||||
val extAddrMap = p(ExtAddrMap)
|
||||
|
||||
val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
|
||||
mmioNetwork.io.in.head <> outmemsys.io.mmio
|
||||
|
||||
val plic = Module(new PLIC(p(PLICKey)))
|
||||
plic.io.tl <> mmioNetwork.port("int:plic")
|
||||
for (i <- 0 until io.interrupts.size) {
|
||||
val gateway = Module(new LevelGateway)
|
||||
gateway.io.interrupt := io.interrupts(i)
|
||||
plic.io.devices(i) <> gateway.io.plic
|
||||
}
|
||||
|
||||
val debugModule = Module(new DebugModule)
|
||||
debugModule.io.tl <> mmioNetwork.port("int:debug")
|
||||
debugModule.io.db <> io.debugBus
|
||||
|
||||
val prci = Module(new PRCI)
|
||||
prci.io.tl <> mmioNetwork.port("int:prci")
|
||||
io.prci := prci.io.tiles
|
||||
prci.io.rtcTick := Counter(p(RTCPeriod)).inc() // placeholder for real RTC
|
||||
|
||||
for (i <- 0 until nTiles) {
|
||||
prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
|
||||
if (p(UseVM))
|
||||
prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
|
||||
prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
|
||||
|
||||
io.prci(i).reset := reset
|
||||
}
|
||||
|
||||
val bootROM = Module(new ROMSlave(makeBootROM()))
|
||||
bootROM.io <> mmioNetwork.port("int:bootrom")
|
||||
val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, extAddrMap))
|
||||
mmioNetwork.io.in.head <> io.mmio_in.get
|
||||
|
||||
for (device <- p(ExtraDevices)) {
|
||||
device.builder(mmioNetwork.port("int:" + device.addrMapEntry.name), io.extra, p)
|
||||
device.builder(mmioNetwork.port(device.addrMapEntry.name), io.extra, p)
|
||||
}
|
||||
|
||||
val ext = p(ExtMMIOPorts).entries.map(port => TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost"))
|
||||
val ext = p(ExtMMIOPorts).map(
|
||||
port => TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost"))
|
||||
connectExternalMMIO(ext)(outermostMMIOParams)
|
||||
}
|
||||
}
|
||||
|
||||
abstract class AbstractOuterMemorySystem(implicit val p: Parameters)
|
||||
extends Module with HasTopLevelParameters {
|
||||
val io = new Bundle {
|
||||
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
|
||||
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
|
||||
val incoherent = Vec(nCachedTilePorts, Bool()).asInput
|
||||
val mem_axi = Vec(nMemAXIChannels, new NastiIO)
|
||||
val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
|
||||
val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
|
||||
val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
|
||||
val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
|
||||
}
|
||||
}
|
||||
|
||||
/** Use in place of OuterMemorySystem if there are no clients to connect. */
|
||||
class DummyOuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySystem()(p) {
|
||||
require(nCachedTilePorts + nUncachedTilePorts == 0)
|
||||
|
||||
io.mem_axi.foreach { axi =>
|
||||
axi.ar.valid := Bool(false)
|
||||
axi.aw.valid := Bool(false)
|
||||
axi.w.valid := Bool(false)
|
||||
axi.r.ready := Bool(false)
|
||||
axi.b.ready := Bool(false)
|
||||
if (exportMMIO) {
|
||||
buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"}))
|
||||
}
|
||||
|
||||
io.mem_ahb.foreach { ahb =>
|
||||
ahb.htrans := UInt(0)
|
||||
ahb.hmastlock := Bool(false)
|
||||
ahb.hwrite := Bool(false)
|
||||
ahb.haddr := UInt(0)
|
||||
ahb.hburst := UInt(0)
|
||||
ahb.hsize := UInt(0)
|
||||
ahb.hprot := UInt(0)
|
||||
}
|
||||
|
||||
io.mem_tl.foreach { tl =>
|
||||
tl.acquire.valid := Bool(false)
|
||||
tl.grant.ready := Bool(false)
|
||||
}
|
||||
|
||||
io.mmio.acquire.valid := Bool(false)
|
||||
io.mmio.grant.ready := Bool(false)
|
||||
}
|
||||
|
||||
/** The whole outer memory hierarchy, including a NoC, some kind of coherence
|
||||
* manager agent, and a converter from TileLink to MemIO.
|
||||
*/
|
||||
class OuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySystem()(p) {
|
||||
// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
|
||||
// Cached ports are first in client list, making sharerToClientId just an indentity function
|
||||
// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
|
||||
def sharerToClientId(sharerId: UInt) = sharerId
|
||||
def addrToBank(addr: UInt): UInt = {
|
||||
val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
|
||||
Mux(isMemory,
|
||||
if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
|
||||
UInt(nBanks))
|
||||
}
|
||||
val preBuffering = TileLinkDepths(1,1,2,2,0)
|
||||
val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
|
||||
|
||||
// Create point(s) of coherence serialization
|
||||
val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
|
||||
managerEndpoints.foreach { _.incoherent := io.incoherent }
|
||||
|
||||
val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
|
||||
case TLId => "L1toL2"
|
||||
case InnerTLId => "L1toL2"
|
||||
case OuterTLId => "L2toMMIO"
|
||||
})))
|
||||
io.mmio <> mmioManager.io.outer
|
||||
|
||||
val bus_in = io.bus_axi.map { ext_nasti =>
|
||||
val converter = Module(new TileLinkIONastiIOConverter)
|
||||
converter.io.nasti <> ext_nasti
|
||||
converter.io.tl
|
||||
}
|
||||
|
||||
// Wire the tiles to the TileLink client ports of the L1toL2 network,
|
||||
// and coherence manager(s) to the other side
|
||||
l1tol2net.io.clients_cached <> io.tiles_cached
|
||||
l1tol2net.io.clients_uncached <> io.tiles_uncached ++ bus_in
|
||||
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
|
||||
|
||||
// Create a converter between TileLinkIO and MemIO for each channel
|
||||
val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
|
||||
val outermostTLParams = p.alterPartial({case TLId => "Outermost"})
|
||||
val backendBuffering = TileLinkDepths(0,0,0,0,0)
|
||||
|
||||
// TODO: the code to print this stuff should live somewhere else
|
||||
println("Generated Address Map")
|
||||
for ((name, region) <- p(GlobalAddrMap).flatten) {
|
||||
println(f"\t$name%s ${region.start}%x - ${region.start + region.size - 1}%x")
|
||||
}
|
||||
println("Generated Configuration String")
|
||||
println(new String(p(ConfigString)))
|
||||
|
||||
val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostTLParams))
|
||||
|
||||
for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
|
||||
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
|
||||
unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
|
||||
TileLinkWidthAdapter(icPort, unwrap.io.out)
|
||||
}
|
||||
|
||||
for ((nasti, tl) <- io.mem_axi zip mem_ic.io.out) {
|
||||
TopUtils.connectTilelinkNasti(nasti, tl)(outermostTLParams)
|
||||
for ((nasti, tl) <- io.mem_axi zip io.mem_in) {
|
||||
TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams)
|
||||
// Memory cache type should be normal non-cacheable bufferable
|
||||
// TODO why is this happening here? Would 0000 (device) be OK instead?
|
||||
nasti.ar.bits.cache := UInt("b0011")
|
||||
nasti.aw.bits.cache := UInt("b0011")
|
||||
}
|
||||
|
||||
|
||||
// Abuse the fact that zip takes the shorter of the two lists
|
||||
for ((ahb, tl) <- io.mem_ahb zip mem_ic.io.out) {
|
||||
for ((ahb, tl) <- io.mem_ahb zip io.mem_in) {
|
||||
val bridge = Module(new AHBBridge(false)) // no atomics
|
||||
ahb <> bridge.io.ahb
|
||||
bridge.io.tl <> tl
|
||||
}
|
||||
|
||||
for ((mem_tl, tl) <- io.mem_tl zip mem_ic.io.out) {
|
||||
for ((mem_tl, tl) <- io.mem_tl zip io.mem_in) {
|
||||
TopUtils.connectTilelink(mem_tl, tl)
|
||||
}
|
||||
}
|
||||
|
||||
@@ -69,7 +69,10 @@ class WithComparator extends Config(
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new ComparatorCore()(p))
|
||||
case ComparatorKey => ComparatorParameters(
|
||||
targets = Seq("mem", "io:int:testram").map(name => site(GlobalAddrMap)(name).start.longValue),
|
||||
targets = Seq(
|
||||
site(GlobalAddrMap)("mem"),
|
||||
site(ExtAddrMap)("testram"))
|
||||
.map(entry => entry.start.longValue),
|
||||
width = 8,
|
||||
operations = 1000,
|
||||
atomics = site(UseAtomics),
|
||||
|
||||
Reference in New Issue
Block a user