allow extra devices and top-level ports to be added without changing RocketChip.scala

src/main/scala/Configs.scala

@@ -34,7 +34,7 @@ class BaseConfig extends Config (
       entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
       entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
       entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
-      entries ++= site(ExtraMMIODevices).entries
+      entries ++= site(ExtraDevices).map(_.addrMapEntry)
       new AddrMap(entries)
     }
     lazy val globalAddrMap = {
@@ -95,12 +95,10 @@ class BaseConfig extends Config (
         res append  "    };\n"
         res append  "  };\n"
       }
-      for (device <- site(ExtraMMIODevices).entries) {
-        val deviceEntry = addrMap("io:int:" + device.name)
-        res append s"  ${device.name} {\n"
-        res append s"    addr 0x${deviceEntry.start.toString(16)};\n"
-        res append s"    size 0x${deviceEntry.size.toString(16)};\n"
-        res append s"  };\n"
+      for (device <- site(ExtraDevices)) {
+        val deviceName = device.addrMapEntry.name
+        val deviceRegion = addrMap("io:int:" + deviceName)
+        res.append(device.makeConfigString(deviceRegion))
       }
       res append  "};\n"
       res append '\u0000'
@@ -231,7 +229,8 @@ class BaseConfig extends Config (
       }
       case NExtInterrupts => 2
       case AsyncMMIOChannels => false
-      case ExtraMMIODevices => AddrMap()
+      case ExtraDevices => Nil
+      case ExtraTopPorts => (p: Parameters) => new Bundle
       case ExtMMIOPorts => AddrMap()
 /*
         AddrMap(
@@ -617,6 +616,15 @@ class TinyConfig extends Config(
 
 class WithTestRAM extends Config(
   (pname, site, here) => pname match {
-    case ExtraMMIODevices => AddrMap(
-      AddrMapEntry("testram", MemSize(0x1000, MemAttr(AddrMapProt.RW))))
+    case ExtraDevices => {
+      class TestRAMDevice extends Device {
+        val ramSize = 0x1000
+        def builder(port: ClientUncachedTileLinkIO, extra: Bundle, p: Parameters) {
+          val testram = Module(new TileLinkTestRAM(ramSize)(p))
+          testram.io <> port
+        }
+        def addrMapEntry = AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW)))
+      }
+      Seq(new TestRAMDevice)
+    }
   })

src/main/scala/DeviceSet.scala

@@ -1,32 +0,0 @@
-package rocketchip
-
-import Chisel.log2Ceil
-import cde.{Parameters, Field}
-import scala.collection.mutable.HashMap
-import junctions._
-
-case object GlobalDeviceSet extends Field[DeviceSet]
-
-case class Device(name: String, size: Int, dtype: String,
-  readable: Boolean = true, writeable: Boolean = true)
-
-class DeviceSet {
-  val deviceMap = new HashMap[String, Device]()
-
-  def addDevice(name: String, size: Int, dtype: String, readable: Boolean = true, writeable: Boolean = true): Unit =
-      addDevice(Device(name, size, dtype, readable, writeable))
-
-  def addDevice(dev: Device): Unit =
-    deviceMap(dev.name) = dev
-
-  def toSeq: Seq[Device] = deviceMap.values.toSeq
-
-  def getAddrMap: AddrMap = {
-    val devices = this.toSeq.sortWith((a, b) => a.size > b.size)
-    val entries = devices.map { case Device(name, size, _, readable, writeable) =>
-      val prot = (if (readable) AddrMapProt.R else 0) | (if (writeable) AddrMapProt.W else 0)
-      AddrMapEntry(name, MemSize(size, MemAttr(prot)))
-    }
-    new AddrMap(entries)
-  }
-}

src/main/scala/Devices.scala

@@ -0,0 +1,20 @@
+package rocketchip
+
+import Chisel._
+import junctions._
+import uncore.tilelink._
+import cde.{Parameters, Field}
+
+case object ExtraTopPorts extends Field[Parameters => Bundle]
+case object ExtraDevices extends Field[Seq[Device]]
+
+abstract class Device {
+  def builder(port: ClientUncachedTileLinkIO, extra: Bundle, p: Parameters): Unit
+  def addrMapEntry: AddrMapEntry
+  def makeConfigString(region: MemRegion): String = {
+    s"  ${addrMapEntry.name} {\n" +
+    s"    addr 0x${region.start.toString(16)};\n" +
+    s"    size 0x${region.size.toString(16)}; \n" +
+     "  }\n"
+  }
+}

src/main/scala/RocketChip.scala

@@ -56,7 +56,6 @@ case object PLICKey extends Field[PLICConfig]
 /** Number of clock cycles per RTC tick */
 case object RTCPeriod extends Field[Int]
 case object AsyncDebugBus extends Field[Boolean]
-case object ExtraMMIODevices extends Field[AddrMap]
 
 /** Utility trait for quick access to some relevant parameters */
 trait HasTopLevelParameters {
@@ -110,6 +109,7 @@ class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
   val debug_clk = if (p(AsyncDebugBus)) Some(Clock(INPUT)) else None
   val debug_rst = if (p(AsyncDebugBus)) Some(Bool(INPUT)) else None
   val debug = new DebugBusIO()(p).flip
+  val extra = p(ExtraTopPorts)(p)
 }
 
 object TopUtils {
@@ -205,6 +205,8 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
     (if (p(AsyncBusChannels))
       asyncAxiFrom(io.bus_clk.get, io.bus_rst.get, io.bus_axi)
     else io.bus_axi)
+
+  io.extra <> uncore.io.extra
 }
 
 /** Wrapper around everything that isn't a Tile.
@@ -227,6 +229,7 @@ class Uncore(implicit val p: Parameters) extends Module
     val mmio_tl  = Vec(p(NExtMMIOTLChannels),  new ClientUncachedTileLinkIO()(outermostMMIOParams))
     val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
     val debugBus = new DebugBusIO()(p).flip
+    val extra = p(ExtraTopPorts)(p)
   }
 
   val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0)
@@ -325,10 +328,8 @@ class Uncore(implicit val p: Parameters) extends Module
     val bootROM = Module(new ROMSlave(makeBootROM()))
     bootROM.io <> mmioNetwork.port("int:bootrom")
 
-    if (ioAddrMap.contains("int:testram")) {
-      val ramSize = ioAddrMap("int:testram").size.intValue
-      val testram = Module(new TileLinkTestRAM(ramSize))
-      testram.io <> mmioNetwork.port("int:testram")
+    for (device <- p(ExtraDevices)) {
+      device.builder(mmioNetwork.port("int:" + device.addrMapEntry.name), io.extra, p)
     }
 
     val ext = p(ExtMMIOPorts).entries.map(port => TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost"))