riscv/rocket-chip
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don't repeat external addr map base

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This commit is contained in:
Howard Mao 2016-08-09 21:20:54 -07:00
parent 3ea2f4a6c4
commit 33f13d5c49
2 changed files with 8 additions and 4 deletions
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10
junctions/src/main/scala/addrmap.scala
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@ -78,15 +78,16 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
def isEmpty = entries.isEmpty
def length = entries.size
def numSlaves = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
def attr = ???
private val slavePorts = HashMap[String, Int]()
private val mapping = HashMap[String, MemRegion]()
val (size: BigInt, entries: Seq[AddrMapEntry]) = {
val (size: BigInt, entries: Seq[AddrMapEntry], attr: MemAttr) = {
var ind = 0
var base = start
var rebasedEntries = collection.mutable.ArrayBuffer[AddrMapEntry]()
var prot = 0
var cacheable = true
for (AddrMapEntry(name, r) <- entriesIn) {
if (r.start != 0) {
val align = BigInt(1) << log2Ceil(r.size)
@ -112,8 +113,10 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
ind += r.numSlaves
base += r.size
prot |= r.attr.prot
cacheable &&= r.attr.cacheable
}
(base - start, rebasedEntries)
(base - start, rebasedEntries, MemAttr(prot, cacheable))
}
val flatten: Seq[(String, MemRange)] = {
@ -123,6 +126,7 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
arr
}
def toRange: MemRange = MemRange(start, size, attr)
def apply(name: String): MemRegion = mapping(name)
def contains(name: String): Boolean = mapping.contains(name)
def port(name: String): Int = slavePorts(name)

2
src/main/scala/Configs.scala
View File

@ -41,7 +41,7 @@ class BaseConfig extends Config (
val memSize = 0x10000000L
val intern = AddrMapEntry("int", internalIOAddrMap)
val extern = AddrMapEntry("ext", MemRange(0x50000000L, 0x30000000L, MemAttr(AddrMapProt.RWX)))
val extern = AddrMapEntry("ext", site(ExtAddrMap).toRange)
val ioMap = if (site(ExportMMIOPort)) AddrMap(intern, extern) else AddrMap(intern)
val addrMap = AddrMap(