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Commit Graph

77 Commits

Author SHA1 Message Date
Andrew Waterman
5164f947c0 Validate mstatus.mpp/dcsr.prv values on MRET/DRET
The registers can still hold invalid values, but an attempt to switch
to the mode stored therein will instead go to an implemented mode.
2016-08-17 15:39:34 -07:00
Howard Mao
38e0967816 strip DMA and RoCC CSRs out of rocket and uncore (#201) 2016-08-15 23:08:55 -07:00
Andrew Waterman
832e56d3c7 Fix toBits/toUInt/toSInt deprecation warnings 2016-07-31 17:13:52 -07:00
Andrew Waterman
ffac86b041 [rocket] only write badaddr on certain exceptions 2016-07-29 17:56:42 -07:00
Howard Mao
51edd19e85 add U bit to misa register 2016-07-22 14:22:59 -07:00
Andrew Waterman
3d0b92afd7 Misc code cleanup 2016-07-14 12:09:34 -07:00
Andrew Waterman
3d8939d3c3 Set misa.base = 1 for RV32 2016-07-07 15:32:21 -07:00
Andrew Waterman
2455a806af Make WFI instruction respect mie CSR setting 2016-07-07 15:31:17 -07:00
Andrew Waterman
f3e22984d5 Remove uarch counters
These will be replaced with the indirect TDR scheme used by breakpoints.
2016-07-06 01:41:41 -07:00
Andrew Waterman
8bd7e3932b Implement priv-1.9 PTE scheme 2016-07-05 19:19:49 -07:00
Howard Mao
a9e0a5e2df changes to imports after uncore refactor 2016-06-28 14:09:31 -07:00
Andrew Waterman
6d43c0a945 Mask interrupts during single-step 2016-06-23 00:01:06 -07:00
Andrew Waterman
60bddddfe6 Merge sptbr and sasid 2016-06-17 18:29:05 -07:00
Andrew Waterman
0b4c8e9af7 Add D-mode single-step support 2016-06-15 16:21:24 -07:00
Andrew Waterman
e3b4b55836 Refactor breakpoints and support range comparison (currently disabled) 2016-06-10 19:55:58 -07:00
Andrew Waterman
c8c7246cce Update breakpoint spec 2016-06-09 19:07:21 -07:00
Andrew Waterman
c85ea7b987 Set badaddr on breakpoints 2016-06-09 12:33:43 -07:00
Andrew Waterman
4cd77cef10 Make dcsr.halt writable 2016-06-09 12:30:09 -07:00
Andrew Waterman
e3c17b5f74 Add provisional breakpoint support 2016-06-08 20:19:52 -07:00
Andrew Waterman
4f2e2480a8 When exceptions occur in D-mode, set pc=0x808, not 0x800
Closes #43
2016-06-06 20:57:22 -07:00
Andrew Waterman
3b0c1ed0c3 Cope with changes to AddrMap 2016-06-03 13:50:29 -07:00
Andrew Waterman
9949347569 First stab at debug interrupts 2016-06-01 16:57:10 -07:00
Andrew Waterman
00ea9a7d82 Remove most of mstatus when user mode isn't supported 2016-05-25 15:37:32 -07:00
Andrew Waterman
335e2c8a1e Support disabling atomics extension 2016-05-24 15:05:41 -07:00
Howard Mao
5cbcc41515 get rid of unused imports 2016-05-02 18:23:46 -07:00
Andrew Waterman
f784f4da93 Rename PRCICoreIO to PRCITileIO 2016-05-02 18:08:01 -07:00
Andrew Waterman
000e20f937 Remove MIPI; make mip.MSIP read-only
The PRCI block outside the core will provide IPIs eventually
2016-05-02 15:18:41 -07:00
Andrew Waterman
83fa489cef Stop using HTIF CSR port
The port itself is still present to keep other stuff compiling.
2016-05-02 14:40:52 -07:00
Andrew Waterman
491184a8f8 ERET -> xRET; remove mcfgaddr 2016-04-30 17:32:51 -07:00
Andrew Waterman
cae4265f3b Change mcfgaddr pointer 2016-04-28 16:14:05 -07:00
Andrew Waterman
739cf07637 Remove mtime/mtimecmp
The RTC is now a device that lives on the MMIO bus.
2016-04-27 14:54:51 -07:00
Andrew Waterman
5fd5b58743 Remove stats CSR 2016-04-26 15:31:32 -07:00
Howard Mao
b7527268bb use address map instead of MMIOBase to find size of memory 2016-04-21 18:44:39 -07:00
Andrew Waterman
adb7eacf6e Fix Chisel3 build for XLen=32 2016-03-30 22:48:51 -07:00
Andrew Waterman
8ad8e8a691 Add partial Sv48/Sv57 support
Right now, we don't support Sv39 and Sv48 at the same time, which needs
to change.
2016-03-30 11:02:22 -07:00
Andrew Waterman
7ae44d4905 Add RV32 support 2016-03-10 17:32:00 -08:00
Andrew Waterman
82c595d11a Fix no-FPU elaboration of CSR file 2016-03-10 17:30:56 -08:00
Andrew Waterman
bc15e8649e WIP on priv spec v1.9 2016-03-02 23:29:58 -08:00
Howard Mao
78579672d3 make mtvec configurable and writeable 2016-01-29 14:51:56 -08:00
Howard Mao
305185c034 send DMA requests through MMIO and get responses through CSRs 2016-01-29 14:51:56 -08:00
Howard Mao
120361226d fix more Chisel3 deprecations 2016-01-14 14:46:31 -08:00
Andrew Waterman
00d17abd78 Don't ignore data value when writing MIPI 2016-01-12 16:23:06 -08:00
Andrew Waterman
5294e94794 Remove CSR back pressure ability
We were using it for IPIs, but no longer need it.
2015-11-24 18:28:14 -08:00
Andrew Waterman
0f092b9b59 Remove IPI network
This is now provided via MMIO.
2015-11-16 21:51:43 -08:00
Yunsup Lee
c7235fecb5 further state optimization in CSRfile when not UseVM 2015-10-25 10:23:46 -07:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Henry Cook
1a1185be3f Vectorize ROCC and Tile memory interfaces 2015-10-20 15:02:24 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Andrew Waterman
f8a7a80644 Make perf counters optional 2015-09-28 13:55:23 -07:00
Howard Mao
d89bcd3922 modify csr file to bring in line with HTIF changes 2015-09-22 10:10:57 -07:00