Validate mstatus.mpp/dcsr.prv values on MRET/DRET
The registers can still hold invalid values, but an attempt to switch to the mode stored therein will instead go to an implemented mode.
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@ -144,6 +144,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reset_mstatus.prv := PRV.M
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val reg_mstatus = Reg(init=reset_mstatus)
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val new_prv = Wire(init = reg_mstatus.prv)
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reg_mstatus.prv := legalizePrivilege(new_prv)
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val reset_dcsr = Wire(init=new DCSR().fromBits(0))
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reset_dcsr.xdebugver := 1
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reset_dcsr.prv := PRV.M
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@ -400,7 +403,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_debug := true
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reg_dpc := epc
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reg_dcsr.cause := Mux(reg_singleStepped, UInt(4), Mux(causeIsDebugInt, UInt(3), UInt(1)))
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reg_dcsr.prv := reg_mstatus.prv
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reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)
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}.elsewhen (delegate) {
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reg_sepc := epc
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reg_scause := cause
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@ -408,33 +411,33 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_mstatus.spie := pie
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reg_mstatus.spp := reg_mstatus.prv
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reg_mstatus.sie := false
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reg_mstatus.prv := PRV.S
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new_prv := PRV.S
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}.otherwise {
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reg_mepc := epc
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reg_mcause := cause
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when (write_badaddr) { reg_mbadaddr := io.badaddr }
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reg_mstatus.mpie := pie
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reg_mstatus.mpp := reg_mstatus.prv
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reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
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reg_mstatus.mie := false
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reg_mstatus.prv := PRV.M
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new_prv := PRV.M
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}
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}
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when (insn_ret) {
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when (Bool(p(UseVM)) && !csr_addr_priv(1)) {
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when (reg_mstatus.spp.toBool) { reg_mstatus.sie := reg_mstatus.spie }
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reg_mstatus.spie := false
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reg_mstatus.spp := PRV.U
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reg_mstatus.prv := reg_mstatus.spp
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new_prv := reg_mstatus.spp
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}.elsewhen (csr_debug) {
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reg_mstatus.prv := reg_dcsr.prv
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new_prv := reg_dcsr.prv
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reg_debug := false
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}.otherwise {
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when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie }
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.elsewhen (Bool(usingVM) && reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie }
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reg_mstatus.mpie := false
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reg_mstatus.mpp := PRV.U
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reg_mstatus.prv := reg_mstatus.mpp
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reg_mstatus.mpp := legalizePrivilege(PRV.U)
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new_prv := reg_mstatus.mpp
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}
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}
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@ -450,18 +453,16 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_fflags := reg_fflags | io.fcsr_flags.bits
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}
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val supportedModes = Vec((PRV.M +: (if (usingUser) Some(PRV.U) else None) ++: (if (usingVM) Seq(PRV.S) else Nil)).map(UInt(_)))
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when (wen) {
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when (decoded_addr(CSRs.mstatus)) {
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val new_mstatus = new MStatus().fromBits(wdata)
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reg_mstatus.mie := new_mstatus.mie
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reg_mstatus.mpie := new_mstatus.mpie
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if (supportedModes.size > 1) {
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if (usingUser) {
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reg_mstatus.mprv := new_mstatus.mprv
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when (supportedModes contains new_mstatus.mpp) { reg_mstatus.mpp := new_mstatus.mpp }
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if (supportedModes.size > 2) {
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reg_mstatus.mpp := trimPrivilege(new_mstatus.mpp)
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if (usingVM) {
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reg_mstatus.mxr := new_mstatus.mxr
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reg_mstatus.pum := new_mstatus.pum
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reg_mstatus.spp := new_mstatus.spp
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@ -506,7 +507,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_dcsr.ebreakm := new_dcsr.ebreakm
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if (usingVM) reg_dcsr.ebreaks := new_dcsr.ebreaks
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if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku
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if (supportedModes.size > 1) reg_dcsr.prv := new_dcsr.prv
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if (usingUser) reg_dcsr.prv := trimPrivilege(new_dcsr.prv)
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}
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when (decoded_addr(CSRs.dpc)) { reg_dpc := ~(~wdata | (coreInstBytes-1)) }
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when (decoded_addr(CSRs.dscratch)) { reg_dscratch := wdata }
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@ -554,12 +555,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_dcsr.debugint := io.prci.interrupts.debug
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reg_dcsr.hwbpcount := UInt(p(NBreakpoints))
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if (!usingUser) {
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reg_mstatus.mpp := PRV.M
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reg_mstatus.prv := PRV.M
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reg_mstatus.mprv := false
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}
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reg_sptbr.asid := 0
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reg_tdrselect.reserved := 0
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reg_tdrselect.tdrmode := true // TODO support D-mode breakpoint theft
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@ -581,4 +576,13 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}
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for (bp <- reg_bp drop p(NBreakpoints))
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bp := new BP().fromBits(0)
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def legalizePrivilege(priv: UInt): UInt =
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if (usingVM) Mux(priv === PRV.H, PRV.U, priv)
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else if (usingUser) Fill(2, priv(0))
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else PRV.M
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def trimPrivilege(priv: UInt): UInt =
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if (usingVM) priv
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else legalizePrivilege(priv)
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}
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@ -38,7 +38,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
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val xLen = p(XLen)
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val usingVM = p(UseVM)
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val usingUser = p(UseUser)
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val usingUser = p(UseUser) || usingVM
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val usingDebug = p(UseDebug)
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val usingFPU = p(UseFPU)
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val usingAtomics = p(UseAtomics)
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