riscv/rocket-chip
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1131 Commits

Author SHA1 Message Date
Andrew Waterman
51379621d6 Flush blocking D$ on FENCE.I 2016-05-31 19:27:28 -07:00
Andrew Waterman
3ee5144923 Fix TLB tag check logic when ASIDs are present 2016-05-27 12:24:17 -07:00
Andrew Waterman
c104b57c52 Use BitPat implicit conversion in instruction decoder 2016-05-26 22:23:21 -07:00
Andrew Waterman
96fa1eb6ad Add UInt->BitPat implicit conversion 
This will be removed from Chisel3, so we're putting it here to maintain
compatibility.
 2016-05-26 18:52:53 -07:00
Andrew Waterman
0c50bfcfb3 Work around more zero-width wire cases 2016-05-25 21:47:48 -07:00
Andrew Waterman
40f38dde63 Work around lack of zero-width wires in D$ 2016-05-25 19:44:31 -07:00
Andrew Waterman
00ea9a7d82 Remove most of mstatus when user mode isn't supported 2016-05-25 15:37:32 -07:00
Andrew Waterman
5442b89664 Remove unnecessary muxes in RV32 MulDiv 2016-05-25 14:27:02 -07:00
Andrew Waterman
9aa724706e Don't include RV64 instructions in RV32 decode table 2016-05-25 14:26:45 -07:00
Andrew Waterman
4605b616c1 Fix bug in D$ AMO/storegen logic 2016-05-24 16:26:07 -07:00
Andrew Waterman
5dac7b818d Support set associativity in blocking D$ 2016-05-24 15:45:52 -07:00
Andrew Waterman
e0addb5723 Support uncached AMOs in blocking D$ 2016-05-24 15:45:35 -07:00
Andrew Waterman
f14d87e327 Support larger I$ sets when VM is disabled 2016-05-24 15:44:59 -07:00
Andrew Waterman
3b35c7470e Add uncached support to blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
42f079ce57 JAL requires DW_XPR 
This has been benign so far because of how the logic minimization worked.
 2016-05-24 15:05:41 -07:00
Andrew Waterman
b92c73e361 Add LR/SC to blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
0d93d1a1a0 Clean up pending store logic a bit 2016-05-24 15:05:41 -07:00
Andrew Waterman
0b8de578d4 Add additional D$ store buffering to prevent structural hazards 2016-05-24 15:05:41 -07:00
Andrew Waterman
354cb2d5ec Don't stall I$ response when resolving a branch misprediction 
This avoids a fetch bubble.

Not clear if this is the best way to do it.  Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
 2016-05-24 15:05:41 -07:00
Andrew Waterman
d7790ac6a4 WIP on blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
335e2c8a1e Support disabling atomics extension 2016-05-24 15:05:41 -07:00
Andrew Waterman
765b90f6a4 Stall on D$ lockups less conservatively 2016-05-24 15:05:41 -07:00
Andrew Waterman
a3061047e3 Instantiate blocking D$ when NMSHRS=0 2016-05-24 15:05:41 -07:00
Andrew Waterman
80482890fd Don't rely on tag value for nacks 2016-05-24 15:05:41 -07:00
Wesley W. Terpstra
e19c5e5d2c IOMSHR: support atomic operations 2016-05-24 15:00:50 -07:00
Andrew Waterman
7bc38383de add (non-working) blocking data cache 2016-05-20 18:59:05 -07:00
Howard Mao
f228309bd1 add assertion to make sure SimpleHellaCacheIF doesn't get exception 2016-05-20 16:30:27 -07:00
Andrew Waterman
4aef567a80 Fix MMIO bug: replay_next wasn't set 2016-05-13 17:59:53 -07:00
Andrew Waterman
742c05d6a7 Pipeline D$->I$ control paths 
These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
 2016-05-13 17:07:28 -07:00
Colin Schmidt
8fa2de0816 chisel3 fix to RoCC connections honor last connect 2016-05-05 18:09:48 -07:00
Andrew Waterman
9dd23a603a Remove HTIF port 2016-05-03 13:41:58 -07:00
Andrew Waterman
5352497edb MPRV takes effect regardless of privilege mode 2016-05-02 19:53:25 -07:00
Howard Mao
5cbcc41515 get rid of unused imports 2016-05-02 18:23:46 -07:00
Andrew Waterman
f784f4da93 Rename PRCICoreIO to PRCITileIO 2016-05-02 18:08:01 -07:00
Andrew Waterman
000e20f937 Remove MIPI; make mip.MSIP read-only 
The PRCI block outside the core will provide IPIs eventually
 2016-05-02 15:18:41 -07:00
Andrew Waterman
83fa489cef Stop using HTIF CSR port 
The port itself is still present to keep other stuff compiling.
 2016-05-02 14:40:52 -07:00
Albert Ou
0ff4fd0ccd Fix IOMSHR to send finishes for stores 2016-04-30 22:20:29 -07:00
Andrew Waterman
491184a8f8 ERET -> xRET; remove mcfgaddr 2016-04-30 17:32:51 -07:00
Andrew Waterman
5af98145b9 don't signal bad physical address on TLB miss 2016-04-30 17:31:46 -07:00
Andrew Waterman
cae4265f3b Change mcfgaddr pointer 2016-04-28 16:14:05 -07:00
Andrew Waterman
739cf07637 Remove mtime/mtimecmp 
The RTC is now a device that lives on the MMIO bus.
 2016-04-27 14:54:51 -07:00
Andrew Waterman
fb5c38c186 Handle invalidate_lr in cache arbiter, not tile 2016-04-27 11:22:04 -07:00
Andrew Waterman
b99db83e67 Avoid needless Vec generation 2016-04-27 00:28:39 -07:00
Andrew Waterman
8acec8eb36 Remove dead code from BTB 2016-04-27 00:28:12 -07:00
Andrew Waterman
fe8c91f620 Fix IOMSHR state machine bug 
Sending the finish too early causes the CPU response to get dropped.

attn @zhemao
 2016-04-26 15:32:25 -07:00
Andrew Waterman
5fd5b58743 Remove stats CSR 2016-04-26 15:31:32 -07:00
Andrew Waterman
d93677a343 Support larger cache sets when not using VM 2016-04-26 15:31:32 -07:00
Yunsup Lee
5dbf9640e2 Use TLB flush signal to I$ explicitly 2016-04-22 15:41:31 -07:00
Andrew Waterman
84fd45fd77 Pass TLB flush signal to I$ explicitly 2016-04-22 15:20:17 -07:00
Howard Mao
b7527268bb use address map instead of MMIOBase to find size of memory 2016-04-21 18:44:39 -07:00
Christopher Celio
2d6f35525e Added Field[Int] to SFMALatency/DFMALatency params 2016-04-06 14:50:57 -07:00
Andrew Waterman
51e0870e23 Separate I$ and D$ interface signals that span clock cycles 
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
 2016-04-01 19:30:39 -07:00
Andrew Waterman
dc662f28a0 Specify width on s1_pc to avoid width inference problem 2016-04-01 17:28:42 -07:00
Andrew Waterman
72f7f71eb5 No need to allow finishes to be sent in s_refill_resp state 
This is a hold-over from when writebacks needed finish messages.
 2016-04-01 16:19:57 -07:00
Henry Cook
78bc18736e LRSC startvation fix: HellaCache generates its own Finish messages again. 2016-04-01 16:04:25 -07:00
Andrew Waterman
37b9051762 No need to validate npc if BTB is disabled 2016-04-01 15:54:57 -07:00
Andrew Waterman
4480d1e817 Don't compile BTB when nEntries=0 2016-04-01 15:14:45 -07:00
Andrew Waterman
d406dc1231 Remove vestigial BTB enable option 2016-04-01 15:14:34 -07:00
Henry Cook
54dd82ff76 bugfix for WB data buffer 2016-03-31 17:53:49 -07:00
Christopher Celio
1792d01ce1 fix leaky assert in nbdcache 
Squash of #33.
 2016-03-31 15:56:14 -07:00
Andrew Waterman
adb7eacf6e Fix Chisel3 build for XLen=32 2016-03-30 22:48:51 -07:00
Andrew Waterman
70664bbca0 Fix Chisel3 build for UseVM=false 2016-03-30 22:48:31 -07:00
Andrew Waterman
8ad8e8a691 Add partial Sv48/Sv57 support 
Right now, we don't support Sv39 and Sv48 at the same time, which needs
to change.
 2016-03-30 11:02:22 -07:00
Andrew Waterman
e652821962 Use correct kind of TileLink arbiter 
It was "correct" before, but broke Chisel3 build.
 2016-03-28 22:53:47 -07:00
Andrew Waterman
5ce3527b88 Merge pull request #32 from ucb-bar/pr-btb-masking 
separate btb response mask from the frontend mask
 2016-03-26 18:15:14 -07:00
Christopher Celio
f526d380fd separate btb response mask from the frontend mask 
It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
 2016-03-26 05:37:26 -07:00
Andrew Waterman
ed280fb3de Remove empty when statement (???) 2016-03-25 15:52:18 -07:00
Andrew Waterman
1ae6d09751 Slightly ameliorate D$->I$ critical path via scoreboard 2016-03-25 15:29:32 -07:00
Andrew Waterman
a4685a073f Don't instantiate PTW when UseVM=false 2016-03-25 14:17:25 -07:00
Andrew Waterman
27b3cca046 Discover D$, PTW port counts dynamically 
This is a generator, after all...
 2016-03-25 14:16:56 -07:00
Andrew Waterman
8d1ba4d1ec Remove hard-coded XLEN values from D$ 2016-03-24 14:52:12 -07:00
Andrew Waterman
7ae44d4905 Add RV32 support 2016-03-10 17:32:00 -08:00
Andrew Waterman
82c595d11a Fix no-FPU elaboration of CSR file 2016-03-10 17:30:56 -08:00
Andrew Waterman
bc15e8649e WIP on priv spec v1.9 2016-03-02 23:29:58 -08:00
Yunsup Lee
15ac4d317f RoCC PTW refactoring 2016-02-25 17:15:38 -08:00
Christopher Celio
b96343a4e5 [btb] fix mix type error for fetch-width > 1 
closes #24
 2016-02-08 17:41:38 -08:00
Christopher Celio
31dd311aff [fpu] fix rounding mode bug in fdivfsqrt 2016-02-08 17:38:31 -08:00
Howard Mao
5abfd1a4ab make sure to check for region violations in DMA frontend 2016-02-03 15:40:44 -08:00
Howard Mao
78579672d3 make mtvec configurable and writeable 2016-01-29 14:51:56 -08:00
Howard Mao
7937fbf074 fix number of IOMSHRs at 1 2016-01-29 14:51:56 -08:00
Howard Mao
305185c034 send DMA requests through MMIO and get responses through CSRs 2016-01-29 14:51:56 -08:00
Andrew Waterman
58fcc6b7c6 Get rid of useless mux 2016-01-28 11:44:59 -08:00
Howard Mao
d170fcd913 DecoupledHelper is now imported from junctions 2016-01-21 15:38:43 -08:00
Andrew Waterman
52d6b0b1a5 Improve ALU QoR 
Rejigger muxes; share XOR gates between ADD/SUB, XOR, and BEQ.
 2016-01-20 17:42:31 -08:00
Howard Mao
77e068c153 fix Chisel3 compat issue in SimpleHellaCacheIF 2016-01-14 22:42:44 -08:00
Howard Mao
120361226d fix more Chisel3 deprecations 2016-01-14 14:46:31 -08:00
Howard Mao
d51c127646 fix deprecation warnings in rocket.scala 2016-01-13 22:08:06 -08:00
Andrew Waterman
ae98af7077 don't mix SInt/UInt 2016-01-12 16:27:36 -08:00
Andrew Waterman
00d17abd78 Don't ignore data value when writing MIPI 2016-01-12 16:23:06 -08:00
Andrew Waterman
7bf503a275 Remove four integer/FP converters 2016-01-12 16:06:23 -08:00
Andrew Waterman
31d537c405 Add missing cloneType 2016-01-12 15:45:11 -08:00
Howard Mao
13ce91e453 fix Chisel3 compat warnings in ICache and FPU 2016-01-12 12:43:48 -08:00
Howard Mao
05b359d357 support streaming DMA in DMA frontend 2016-01-06 18:17:41 -08:00
Howard Mao
304d8b814a Implement client-side DMA controller 2015-12-16 21:24:24 -08:00
Albert Magyar
01a3447989 Remove duplicate PseudoLRU class from rocket TLB 2015-12-16 16:12:47 -08:00
Howard Mao
7690de07e1 allow icache to configure which side of the way mux gets buffered 2015-12-02 17:17:49 -08:00
Howard Mao
369ee74a2c change names of RoCC tilelink interfaces to be more sensible 2015-12-02 16:28:23 -08:00
Howard Mao
73b0263663 disconnect fpu port if no fpu-using RoCC accelerators 2015-12-01 20:41:58 -08:00
Howard Mao
dcca0b1d86 fix up FPU connection 2015-12-01 18:14:58 -08:00
Howard Mao
08f77ca90d Merge branch 'master' into rocc-fpu-port 2015-12-01 18:00:28 -08:00