riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
3,872 Commits 1 Branch 0 Tags 13 MiB
4b9dc78951
Commit Graph

3872 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Colin Schmidt
b0ae003981 add firrtl to regression makefile 
this makes it easier to test chisel3 builds
e.g. the local buildbot can now test a bunch of configs
 2016-05-17 17:34:20 -07:00
Andrew Waterman
4aef567a80 Fix MMIO bug: replay_next wasn't set 2016-05-13 17:59:53 -07:00
Andrew Waterman
742c05d6a7 Pipeline D$->I$ control paths 
These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
 2016-05-13 17:07:28 -07:00
Andrew Waterman
684d902059 Fix PLIC instantiation when S-mode is disabled 2016-05-13 11:22:46 -07:00
Howard Mao
f138819992 fix order of assignments in ManagerTileLinkNetworkPort 2016-05-11 16:45:00 -07:00
Andrew Waterman
6aa708bcee Disable MMIO by default to avoid disconnected nets 2016-05-11 13:12:39 -07:00
Christopher Celio
3fe00ce32a Update README.md 
- Removed instruction to checkout riscv-tests (as they are now globally installed when building the riscv-tools).
- Clarified the riscv-tools set-up information to clarify that the rocket-chip/riscv-tools is the version to build.
 2016-05-10 22:12:02 -07:00
Andrew Waterman
533b229175 Improve PLIC QoR 2016-05-10 17:03:56 -07:00
Andrew Waterman
fbff46d27d bump rocket 2016-05-10 10:57:03 -07:00
Andrew Waterman
aac89ca1f0 Add PLIC 2016-05-10 00:27:31 -07:00
Andrew Waterman
e15e9c5085 First draft of interrupt controller 2016-05-10 00:25:13 -07:00
Howard Mao
df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
Howard Mao
14a6e470c9 transform ids in TL -> NASTI converter if necessary 2016-05-07 21:19:27 -07:00
Howard Mao
3b0e9167fa add AXI to AHB converter and more conformant HASTI RAM 2016-05-06 11:32:03 -07:00
Howard Mao
3e759d2575 add Hasti test to unit test 2016-05-06 11:31:43 -07:00
Howard Mao
1ed6d6646d move NastiROM and HastiRAM into rom.scala and bram.scala 2016-05-06 11:31:22 -07:00
Howard Mao
77e859760c add a Hasti RAM alongside the Nasti ROM 2016-05-06 11:31:22 -07:00
Howard Mao
44740cb6b2 parameterize Hasti address and data bits 2016-05-06 11:30:50 -07:00
Howard Mao
64991d3947 add AXI to AHB converter 2016-05-06 11:30:50 -07:00
Howard Mao
a875eb9c31 update riscv-tools for bbl fix 2016-05-05 19:36:34 -07:00
Colin Schmidt
8fa2de0816 chisel3 fix to RoCC connections honor last connect 2016-05-05 18:09:48 -07:00
Howard Mao
18ffe7b1ec don't use +verbose in vsim .run rule 2016-05-04 23:01:14 -07:00
Andrew Waterman
8b06947446 Run bmarks faster (hopefully) 2016-05-04 22:47:34 -07:00
Howard Mao
f1baa4aecc update riscv-tests so that mm benchmark doesn't run forever 2016-05-04 21:28:55 -07:00
Howard Mao
dfcb73b6c9 groundtest only needs to write to a single tohost 2016-05-03 20:21:13 -07:00
Howard Mao
1882e694e4 only write to a single tohost location 2016-05-03 20:20:52 -07:00
Howard Mao
4045a07eda Remove need for separate riscv-tests for groundtest 2016-05-03 18:29:46 -07:00
Howard Mao
8f891437b5 fix CacheFillTest 2016-05-03 14:57:05 -07:00
Andrew Waterman
15f4af19cf Remove HTIF CPU port 2016-05-03 13:55:59 -07:00
Andrew Waterman
9dd23a603a Remove HTIF port 2016-05-03 13:41:58 -07:00
Howard Mao
6cb0979ac4 fix CacheFillTest 2016-05-03 13:35:38 -07:00
Howard Mao
487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
Howard Mao
518d510622 only write out finish from tile 0 in groundtest 2016-05-03 13:09:22 -07:00
Howard Mao
f26c422544 assert that TileLink router has valid route 2016-05-03 12:18:06 -07:00
Howard Mao
b95f095aca write to multiple possible tohost locations 2016-05-02 20:11:20 -07:00
Andrew Waterman
5352497edb MPRV takes effect regardless of privilege mode 2016-05-02 19:53:25 -07:00
Howard Mao
4b4e8f7f62 fixes for priv-1.9 changes 2016-05-02 18:25:02 -07:00
Howard Mao
5cbcc41515 get rid of unused imports 2016-05-02 18:23:46 -07:00
Howard Mao
be21f6962b make GlobalAddrHashMap a config variable 2016-05-02 18:22:43 -07:00
Andrew Waterman
c7c8ae5468 Instantiate PRCI block 2016-05-02 18:08:33 -07:00
Andrew Waterman
f784f4da93 Rename PRCICoreIO to PRCITileIO 2016-05-02 18:08:01 -07:00
Andrew Waterman
cc4102f8de Add trivial version of PRCI block 
It doesn't really do anything besides deliver deliver IPIs yet.
 2016-05-02 17:49:10 -07:00
Andrew Waterman
6d1e82bddf Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port 2016-05-02 15:21:55 -07:00
Andrew Waterman
72731de25a Take a stab at the PRCI-Rocket interface 2016-05-02 15:20:33 -07:00
Andrew Waterman
000e20f937 Remove MIPI; make mip.MSIP read-only 
The PRCI block outside the core will provide IPIs eventually
 2016-05-02 15:18:41 -07:00
Andrew Waterman
83fa489cef Stop using HTIF CSR port 
The port itself is still present to keep other stuff compiling.
 2016-05-02 14:40:52 -07:00
Andrew Waterman
c4d2d29e80 Stub out debug module, rather than leaving it floating 2016-04-30 22:37:39 -07:00
Albert Ou
0ff4fd0ccd Fix IOMSHR to send finishes for stores 2016-04-30 22:20:29 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman
695c4c5096 Support both Get and GetBlock on ROMSlave 2016-04-30 17:34:12 -07:00