Howard Mao
0a85e92652
Allow additional internal MMIO devices to be created without changing BaseConfig
2016-08-04 11:04:52 -07:00
Howard Mao
b7723f1ff8
make unit tests local to the packages being tested
2016-08-01 17:02:00 -07:00
Andrew Waterman
832e56d3c7
Fix toBits/toUInt/toSInt deprecation warnings
2016-07-31 17:13:52 -07:00
Howard Mao
59d700bf66
fix combinational loop in NASTI -> HASTI converter
2016-07-15 18:45:37 -07:00
Howard Mao
897e6ccf8a
fix Hasti and Smi converters
2016-07-15 15:39:00 -07:00
Howard Mao
66b9c5ad05
fix up cloneType calls in clock crossers
2016-07-13 14:31:19 -07:00
Wesley W. Terpstra
eeae74e3fc
nasti: include convenient clock crossing helpers
2016-07-13 14:20:25 -07:00
Wesley W. Terpstra
c33c0944be
crossing: first clock crossing, the handshaker
2016-07-13 14:20:25 -07:00
Howard Mao
37fd11870c
fix up ReorderQueue CAM
2016-07-13 12:11:43 -07:00
Howard Mao
c0dc09b3a1
don't use CAM in ReorderQueue if not necessary
2016-07-13 11:08:15 -07:00
Palmer Dabbelt
2f70136f90
Fix the Nasti to Smi Converter for single-word Nasti busses
...
There's a register that tracks what word within a Nasti transaction a
Smi response cooresponds to, since Smi itself doesn't have any
multi-word stuff. This breaks the single-word Nasti to Smi converter
due to what's essentially a 0-width wire bug: it ends up doing something
like
word_offset_into_nasti := nasti_address(3, 3)
when "word_offset_into_nasti" should really be a 0-bit register, but due
to some log2Up block size calculation logic it's actually a 1-bit
register. Thus, this expression ends up grabbing a bit of the address,
which causes odd addresses to get buffered incorrectly.
My fix is to just special-case the "Nasti bus width is the same as Smi
bus width" case.
2016-07-12 09:31:21 -07:00
Howard Mao
6055482513
make sure write channel id is actually set
2016-07-07 12:12:39 -07:00
Howard Mao
bbf780725f
add NastiReadIO and NastiWriteIO bundles
2016-07-06 15:13:04 -07:00
Howard Mao
96f09003f2
use options for NastiWriteDataChannel write mask
2016-07-05 16:03:25 -07:00
Wesley W. Terpstra
ed9fcea7f8
hasti: correct fix to locking
2016-06-08 16:28:30 -07:00
Wesley W. Terpstra
ad4e4f19be
Revert "Don't rely on Mux1H output when no inputs are hot"
...
This reverts commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970.
2016-06-08 16:28:30 -07:00
Wesley W. Terpstra
3393d4362b
hasti: fix test SRAM depth
2016-06-08 16:28:30 -07:00
Howard Mao
0969be8804
Revert "make sure SlowIO clock divider is initialized on reset"
...
This reverts commit 546aaad8cfb03e45e068733c2b694232bcf9dcdb.
2016-06-08 13:45:30 -07:00
Howard Mao
636a46c052
make sure SlowIO clock divider is initialized on reset
2016-06-08 10:02:21 -07:00
Andrew Waterman
28161cab45
Merge AddrHashMap and AddrMap
2016-06-03 13:46:53 -07:00
Wesley W. Terpstra
695be2f0ae
hasti: work-around unsupported 0-width signals
2016-06-01 16:38:49 -07:00
Howard Mao
8983b0e865
hopefully the last fix for AXI -> AHB converter
2016-06-01 15:01:52 -07:00
Howard Mao
53a0e6cb9c
another fix for AXI -> AHB converter
2016-06-01 11:35:36 -07:00
Howard Mao
d0988902f2
fix NASTI -> HASTI bridge
2016-05-31 19:47:50 -07:00
Andrew Waterman
56897f707a
Don't rely on Mux1H output when no inputs are hot
2016-05-27 13:38:01 -07:00
Andrew Waterman
056d7ec93a
Drive hmastlock low in Nasti-Hasti converter
2016-05-27 12:23:18 -07:00
Andrew Waterman
e036d3a04a
Chisel3: gender issue
2016-05-26 15:59:08 -07:00
Andrew Waterman
a2b9d337b6
No need for full-throughput queues in NastiErrorSlave
2016-05-26 01:03:40 -07:00
Andrew Waterman
2ece3e6102
Use Mem for ReorderQueue data
...
This might improve FPGA QoR.
2016-05-26 01:02:56 -07:00
Wesley W. Terpstra
1c8745dfd2
ahb: backport to chisel2
...
Merges #16
2016-05-25 12:11:26 -07:00
Donggyu
a9599302bd
fix cloneType in nasti.scala ( #14 )
2016-05-24 17:10:17 -07:00
Wesley W. Terpstra
b921bae107
ahb: eliminate trait abused for constants
2016-05-24 14:20:45 -07:00
Wesley W. Terpstra
200c69c106
ahb: support hmastlock acquistion of crossbar
2016-05-24 14:20:45 -07:00
Wesley W. Terpstra
e1e8eda419
ahb: add a test SRAM
2016-05-24 14:20:42 -07:00
Wesley W. Terpstra
1db40687c6
ahb: eliminate now-unnecesary non-standard hreadyin
2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
15cad8414d
ahb: put signals in the order they appear in signal traces in the spec
2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
f30f8d9f79
ahb: reduce obsolete degenerate cases of a crossbar
2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
0368b6db6b
ahb: replace defective crossbar with a functional one
...
The previous crossbar had the following bugs:
1. a bursting master could be preempted
the AHB-lite spec requires a slave receive the entire burst
2. a waited master could be replaced
the AHB-lite spec requires haddr/etc to remain unchanged
3. hmastlock did no ensure exclusive access
atomic operations could be pre-empted
2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
2b37f37335
ahb: helper methods
2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
ef2aae26a8
ahb: rename hreadyout to standard hready, mark hreadyin for death
2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
2f8a77f27a
ahb: include all AHB-lite constants
2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
7896c4157e
ahb: parameterize poci
2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
93447eb274
ahb: make hasti parameters location sensitive
2016-05-24 14:14:17 -07:00
Howard Mao
44740cb6b2
parameterize Hasti address and data bits
2016-05-06 11:30:50 -07:00
Howard Mao
64991d3947
add AXI to AHB converter
2016-05-06 11:30:50 -07:00
Howard Mao
be21f6962b
make GlobalAddrHashMap a config variable
2016-05-02 18:22:43 -07:00
Andrew Waterman
e4ace55d77
Address Map refactoring
2016-04-28 16:12:35 -07:00
Andrew Waterman
c8b1f0801b
Remove start address option from AddrMapEntries
...
It appears to never be used, and clutters things. The new invariant is
that AddrMaps are relative and AddrHashMaps are absolute.
2016-04-27 14:52:05 -07:00
Andrew Waterman
d3dee2c6c6
support countSlaves on empty address maps
2016-04-27 14:51:52 -07:00
Howard Mao
6260ad56e8
stop using MMIOBase and encode cacheability in address map
2016-04-21 15:33:53 -07:00
