2f70136f90
There's a register that tracks what word within a Nasti transaction a Smi response cooresponds to, since Smi itself doesn't have any multi-word stuff. This breaks the single-word Nasti to Smi converter due to what's essentially a 0-width wire bug: it ends up doing something like word_offset_into_nasti := nasti_address(3, 3) when "word_offset_into_nasti" should really be a 0-bit register, but due to some log2Up block size calculation logic it's actually a 1-bit register. Thus, this expression ends up grabbing a bit of the address, which causes odd addresses to get buffered incorrectly. My fix is to just special-case the "Nasti bus width is the same as Smi bus width" case. |
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| .. | ||
| project | ||
| src/main/scala | ||
| .gitignore | ||
| build.sbt | ||
| LICENSE | ||
| README.md | ||
junctions
A repository for peripheral components and IO devices associated with the RocketChip project.
To uses these modules, include this repo as a git submodule within the your chip repository and add it as Project in your chip's build.scala. These components are only dependent on Chisel, i.e.
lazy val junctions = project.dependsOn(chisel)