make unit tests local to the packages being tested
This commit is contained in:
Howard Mao
163
junctions/src/main/scala/unittests/MiscNastiTests.scala
Normal file
163
junctions/src/main/scala/unittests/MiscNastiTests.scala
Normal file
@ -0,0 +1,163 @@
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package junctions.unittests
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import cde.Parameters
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class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
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(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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val nasti = new NastiIO
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val finished = Bool(OUTPUT)
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val start = Bool(INPUT)
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}
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val dataBytes = dataWidth / 8
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val nastiDataBytes = nastiXDataBits / 8
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val (write_cnt, write_done) = Counter(io.nasti.w.fire(), burstLen)
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val (read_cnt, read_done) = Counter(io.nasti.r.fire(), burstLen)
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val (req_cnt, reqs_done) = Counter(read_done, nBursts)
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val req_addr = Cat(req_cnt, UInt(0, log2Up(burstLen * dataBytes)))
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val write_data = UInt(0x10000000L, dataWidth) | Cat(req_cnt, write_cnt)
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val expected_data = UInt(0x10000000L, dataWidth) | Cat(req_cnt, read_cnt)
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val (s_idle :: s_write_addr :: s_write_data :: s_write_stall :: s_write_resp ::
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s_read_addr :: s_read_data :: s_read_stall :: s_done :: Nil) = Enum(Bits(), 9)
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val state = Reg(init = s_idle)
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val (stall_cnt, stall_done) = Counter(state === s_read_stall, 2)
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io.nasti.aw.valid := (state === s_write_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = req_addr,
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size = UInt(log2Up(dataBytes)),
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len = UInt(burstLen - 1))
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io.nasti.w.valid := (state === s_write_data)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = Cat(write_data, write_data),
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last = (write_cnt === UInt(burstLen - 1)))
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io.nasti.b.ready := (state === s_write_resp)
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io.nasti.ar.valid := (state === s_read_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = req_addr,
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size = UInt(log2Up(dataBytes)),
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len = UInt(burstLen - 1))
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io.nasti.r.ready := (state === s_read_data)
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io.finished := (state === s_done)
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when (state === s_idle && io.start) { state := s_write_addr }
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when (io.nasti.aw.fire()) { state := s_write_data }
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when (io.nasti.w.fire()) { state := s_write_stall }
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when (state === s_write_stall) { state := s_write_data }
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when (write_done) { state := s_write_resp }
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when (io.nasti.b.fire()) { state := s_read_addr }
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when (io.nasti.ar.fire()) { state := s_read_data }
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when (io.nasti.r.fire()) { state := s_read_stall }
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when (stall_done) { state := s_read_data }
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when (read_done) { state := s_write_addr }
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when (reqs_done) { state := s_done }
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val full_addr = req_addr + (read_cnt << UInt(log2Up(dataBytes)))
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val byteshift = full_addr(log2Up(nastiDataBytes) - 1, 0)
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val bitshift = Cat(byteshift, UInt(0, 3))
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val read_data = (io.nasti.r.bits.data >> bitshift) & Fill(dataWidth, UInt(1, 1))
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assert(!io.nasti.r.valid || read_data === expected_data,
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s"NastiDriver got wrong data")
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}
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class AtosConverterTestBackend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val finished = Bool(OUTPUT)
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}
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val (s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_waddr)
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val n_words = 4
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val test_data = Reg(Vec(n_words, UInt(width = nastiXDataBits)))
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val req_id = Reg(UInt(width = nastiXIdBits))
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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when (io.nasti.aw.fire()) {
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req_id := io.nasti.aw.bits.id
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state := s_wdata
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}
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when (io.nasti.w.fire()) {
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test_data(w_count) := io.nasti.w.bits.data
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when (io.nasti.w.bits.last) { state := s_wresp }
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}
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) {
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req_id := io.nasti.ar.bits.id
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state := s_rresp
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}
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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io.nasti.aw.ready := (state === s_waddr)
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io.nasti.w.ready := (state === s_wdata)
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io.nasti.ar.ready := (state === s_raddr)
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io.nasti.b.valid := (state === s_wresp)
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io.nasti.b.bits := NastiWriteResponseChannel(id = req_id)
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io.nasti.r.valid := (state === s_rresp)
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io.nasti.r.bits := NastiReadDataChannel(
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id = req_id,
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data = test_data(r_count),
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last = r_last)
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io.finished := (state === s_done)
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}
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class AtosConverterTest(implicit val p: Parameters) extends UnitTest
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with HasNastiParameters {
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val frontend = Module(new NastiDriver(nastiXDataBits, 4, 1))
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val backend = Module(new AtosConverterTestBackend)
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val serdes = Module(new AtosSerdes(8))
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val desser = Module(new AtosDesser(8))
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val client_conv = Module(new AtosClientConverter)
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val manager_conv = Module(new AtosManagerConverter)
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client_conv.io.nasti <> frontend.io.nasti
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serdes.io.wide <> client_conv.io.atos
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desser.io.narrow <> serdes.io.narrow
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manager_conv.io.atos <> desser.io.wide
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backend.io.nasti <> manager_conv.io.nasti
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frontend.io.start := io.start
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io.finished := frontend.io.finished && backend.io.finished
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}
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class HastiTest(implicit p: Parameters) extends UnitTest {
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val sram = Module(new HastiTestSRAM(8))
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val bus = Module(new HastiBus(Seq(a => Bool(true))))
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val conv = Module(new HastiMasterIONastiIOConverter)
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val driver = Module(new NastiDriver(32, 8, 2))
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bus.io.slaves(0) <> sram.io
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bus.io.master <> conv.io.hasti
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conv.io.nasti <> driver.io.nasti
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io.finished := driver.io.finished
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driver.io.start := io.start
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}
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85
junctions/src/main/scala/unittests/MultiWidthFifoTest.scala
Normal file
85
junctions/src/main/scala/unittests/MultiWidthFifoTest.scala
Normal file
@ -0,0 +1,85 @@
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package junctions.unittests
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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class MultiWidthFifoTest extends UnitTest {
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val big2little = Module(new MultiWidthFifo(16, 8, 8))
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val little2big = Module(new MultiWidthFifo(8, 16, 4))
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val bl_send = Reg(init = Bool(false))
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val lb_send = Reg(init = Bool(false))
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val bl_recv = Reg(init = Bool(false))
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val lb_recv = Reg(init = Bool(false))
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val bl_finished = Reg(init = Bool(false))
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val lb_finished = Reg(init = Bool(false))
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val bl_data = Vec.tabulate(4){i => UInt((2 * i + 1) * 256 + 2 * i, 16)}
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val lb_data = Vec.tabulate(8){i => UInt(i, 8)}
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val (bl_send_cnt, bl_send_done) = Counter(big2little.io.in.fire(), 4)
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val (lb_send_cnt, lb_send_done) = Counter(little2big.io.in.fire(), 8)
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val (bl_recv_cnt, bl_recv_done) = Counter(big2little.io.out.fire(), 8)
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val (lb_recv_cnt, lb_recv_done) = Counter(little2big.io.out.fire(), 4)
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big2little.io.in.valid := bl_send
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big2little.io.in.bits := bl_data(bl_send_cnt)
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big2little.io.out.ready := bl_recv
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little2big.io.in.valid := lb_send
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little2big.io.in.bits := lb_data(lb_send_cnt)
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little2big.io.out.ready := lb_recv
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val bl_recv_data_idx = bl_recv_cnt >> UInt(1)
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val bl_recv_data = Mux(bl_recv_cnt(0),
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bl_data(bl_recv_data_idx)(15, 8),
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bl_data(bl_recv_data_idx)(7, 0))
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val lb_recv_data = Cat(
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lb_data(Cat(lb_recv_cnt, UInt(1, 1))),
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lb_data(Cat(lb_recv_cnt, UInt(0, 1))))
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when (io.start) {
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bl_send := Bool(true)
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lb_send := Bool(true)
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}
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when (bl_send_done) {
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bl_send := Bool(false)
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bl_recv := Bool(true)
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}
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when (lb_send_done) {
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lb_send := Bool(false)
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lb_recv := Bool(true)
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}
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when (bl_recv_done) {
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bl_recv := Bool(false)
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bl_finished := Bool(true)
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}
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when (lb_recv_done) {
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lb_recv := Bool(false)
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lb_finished := Bool(true)
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}
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io.finished := bl_finished && lb_finished
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val bl_start_recv = Reg(next = bl_send_done)
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val lb_start_recv = Reg(next = lb_send_done)
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assert(!little2big.io.out.valid || little2big.io.out.bits === lb_recv_data,
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"Little to Big data mismatch")
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assert(!big2little.io.out.valid || big2little.io.out.bits === bl_recv_data,
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"Bit to Little data mismatch")
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assert(!lb_start_recv || little2big.io.count === UInt(4),
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"Little to Big count incorrect")
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assert(!bl_start_recv || big2little.io.count === UInt(8),
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"Big to Little count incorrect")
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}
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111
junctions/src/main/scala/unittests/NastiDemuxTest.scala
Normal file
111
junctions/src/main/scala/unittests/NastiDemuxTest.scala
Normal file
@ -0,0 +1,111 @@
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package junctions.unittests
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import cde.Parameters
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class NastiDemuxDriver(n: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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val nasti = new NastiIO
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val select = UInt(OUTPUT, log2Up(n))
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}
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val (s_idle :: s_write_addr :: s_write_data :: s_write_resp ::
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s_read_addr :: s_read_resp :: s_done :: Nil) = Enum(Bits(), 7)
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val state = Reg(init = s_idle)
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val select = Reg(init = UInt(0, log2Up(n)))
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when (state === s_idle && io.start) { state := s_write_addr }
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when (io.nasti.aw.fire()) { state := s_write_data }
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when (io.nasti.w.fire()) { state := s_write_resp }
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when (io.nasti.b.fire()) { state := s_read_addr }
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when (io.nasti.ar.fire()) { state := s_read_resp }
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when (io.nasti.r.fire()) {
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when (select === UInt(n - 1)) {
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state := s_done
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} .otherwise {
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select := select + UInt(1)
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state := s_write_addr
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}
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}
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io.nasti.aw.valid := (state === s_write_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt("b011"))
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io.nasti.w.valid := (state === s_write_data)
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io.nasti.w.bits := NastiWriteDataChannel(data = select)
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io.nasti.b.ready := (state === s_write_resp)
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io.nasti.ar.valid := (state === s_read_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt("b011"))
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io.nasti.r.ready := (state === s_read_resp)
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io.finished := (state === s_done)
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io.select := select
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assert(!io.nasti.r.valid || io.nasti.r.bits.data === select,
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"NASTI DeMux test: Read data did not match")
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}
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class NastiDemuxSlave(implicit p: Parameters) extends NastiModule()(p) {
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val io = (new NastiIO).flip
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val (s_write_wait :: s_write_data :: s_write_resp ::
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s_read_wait :: s_read_resp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_write_wait)
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val value = Reg(UInt(width = 64))
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val id = Reg(UInt(width = nastiXIdBits))
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when (io.aw.fire()) {
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id := io.aw.bits.id
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state := s_write_data
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}
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when (io.w.fire()) {
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value := io.w.bits.data
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state := s_write_resp
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}
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when (io.b.fire()) { state := s_read_wait }
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when (io.ar.fire()) {
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id := io.ar.bits.id
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state := s_read_resp
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}
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when (io.r.fire()) { state := s_done }
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io.aw.ready := (state === s_write_wait)
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io.w.ready := (state === s_write_data)
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io.b.valid := (state === s_write_resp)
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io.b.bits := NastiWriteResponseChannel(id = id)
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io.ar.ready := (state === s_read_wait)
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io.r.valid := (state === s_read_resp)
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io.r.bits := NastiReadDataChannel(id = id, data = value)
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}
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class NastiMemoryDemuxTest(implicit p: Parameters) extends UnitTest {
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val nSlaves = 4
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val driver = Module(new NastiDemuxDriver(nSlaves))
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driver.io.start := io.start
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io.finished := driver.io.finished
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val demux = Module(new NastiMemoryDemux(nSlaves))
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demux.io.master <> driver.io.nasti
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demux.io.select := driver.io.select
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for (i <- 0 until nSlaves) {
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val slave = Module(new NastiDemuxSlave)
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slave.io <> demux.io.slaves(i)
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}
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}
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63
junctions/src/main/scala/unittests/UnitTest.scala
Normal file
63
junctions/src/main/scala/unittests/UnitTest.scala
Normal file
@ -0,0 +1,63 @@
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package junctions.unittests
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import Chisel._
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import junctions._
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import cde.{Field, Parameters}
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abstract class UnitTest extends Module {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val start = Bool(INPUT)
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}
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when (io.start) {
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printf(s"Started UnitTest ${this.getClass.getSimpleName}\n")
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}
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}
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case object UnitTests extends Field[Parameters => Seq[UnitTest]]
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class UnitTestSuite(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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}
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val tests = p(UnitTests)(p)
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val s_idle :: s_start :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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val test_idx = Reg(init = UInt(0, log2Up(tests.size)))
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val test_finished = Vec(tests.map(_.io.finished))
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when (state === s_idle) { state := s_start }
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when (state === s_start) { state := s_wait }
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when (state === s_wait && test_finished(test_idx)) {
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state := s_start
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test_idx := test_idx + UInt(1)
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state := Mux(test_idx === UInt(tests.size - 1), s_done, s_start)
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}
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val timer = Module(new Timer(1000, tests.size))
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tests.zipWithIndex.foreach { case (mod, i) =>
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mod.io.start := (state === s_start) && test_idx === UInt(i)
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when (test_idx === UInt(i)) {
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timer.io.start.valid := mod.io.start
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timer.io.start.bits := UInt(i)
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timer.io.stop.valid := mod.io.finished
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timer.io.stop.bits := UInt(i)
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}
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}
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io.finished := (state === s_done)
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assert(!timer.io.timeout.valid, "UnitTest timed out")
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||||
}
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object JunctionsUnitTests {
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||||
def apply(implicit p: Parameters): Seq[UnitTest] =
|
||||
Seq(
|
||||
Module(new MultiWidthFifoTest),
|
||||
Module(new AtosConverterTest),
|
||||
Module(new NastiMemoryDemuxTest),
|
||||
Module(new HastiTest))
|
||||
}
|
||||
@ -312,3 +312,54 @@ class MultiWidthFifo(inW: Int, outW: Int, n: Int) extends Module {
|
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io.in.ready := size < UInt(n * nBeats)
|
||||
}
|
||||
}
|
||||
|
||||
// ============
|
||||
// Static timer
|
||||
// ============
|
||||
|
||||
// Timer with a statically-specified period.
|
||||
// Can take multiple inflight start-stop events with ID
|
||||
// Will continue to count down as long as at least one event is inflight
|
||||
|
||||
class Timer(initCount: Int, maxInflight: Int) extends Module {
|
||||
val io = new Bundle {
|
||||
val start = Valid(UInt(width = log2Up(maxInflight))).flip
|
||||
val stop = Valid(UInt(width = log2Up(maxInflight))).flip
|
||||
val timeout = Valid(UInt(width = log2Up(maxInflight)))
|
||||
}
|
||||
|
||||
val inflight = Reg(init = Vec.fill(maxInflight) { Bool(false) })
|
||||
val countdown = Reg(UInt(width = log2Up(initCount)))
|
||||
val active = inflight.reduce(_ || _)
|
||||
|
||||
when (active) {
|
||||
countdown := countdown - UInt(1)
|
||||
}
|
||||
|
||||
when (io.start.valid) {
|
||||
inflight(io.start.bits) := Bool(true)
|
||||
countdown := UInt(initCount - 1)
|
||||
}
|
||||
when (io.stop.valid) {
|
||||
inflight(io.stop.bits) := Bool(false)
|
||||
}
|
||||
|
||||
io.timeout.valid := countdown === UInt(0) && active
|
||||
io.timeout.bits := PriorityEncoder(inflight)
|
||||
|
||||
assert(!io.stop.valid || inflight(io.stop.bits),
|
||||
"Timer stop for transaction that's not inflight")
|
||||
}
|
||||
|
||||
object Timer {
|
||||
def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
|
||||
val timer = Module(new Timer(initCount, 1))
|
||||
timer.io.start.valid := start
|
||||
timer.io.start.bits := UInt(0)
|
||||
timer.io.stop.valid := stop
|
||||
timer.io.stop.bits := UInt(0)
|
||||
timer.io.timeout.valid
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user