Fix toBits/toUInt/toSInt deprecation warnings

junctions/src/main/scala/hasti.scala

@@ -467,12 +467,12 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
   val mask_decode = Vec.tabulate(hastiAlignment+1) (UInt(_) <= io.hsize)
   val mask_wide   = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Up(i+1)) }
   val mask_shift  = if (hastiAlignment == 0) UInt(1) else
-                    mask_wide.toBits().asUInt() << io.haddr(hastiAlignment-1,0)
+                    mask_wide.asUInt() << io.haddr(hastiAlignment-1,0)
   
   // The request had better have been aligned! (AHB-lite requires this)
   if (hastiAlignment >= 1) {
     assert (io.htrans === HTRANS_IDLE || io.htrans === HTRANS_BUSY ||
-      (io.haddr & mask_decode.toBits()(hastiAlignment,1).asUInt) === UInt(0),
+      (io.haddr & mask_decode.asUInt()(hastiAlignment,1)) === UInt(0),
       "HASTI request not aligned")
   }
   
@@ -543,7 +543,7 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
                     map { case (m, p) => Mux(d_read && ready && m, p, Bits(0)) })
 
   // Finally, the outputs
-  io.hrdata := outdata.toBits()
+  io.hrdata := outdata.asUInt
   io.hready := ready
   io.hresp  := HRESP_OKAY
 }

junctions/src/main/scala/memserdes.scala

@@ -66,8 +66,8 @@ class MemSerdes(w: Int)(implicit p: Parameters) extends MIFModule
     val wide = new MemIO().flip
     val narrow = new MemSerializedIO(w)
   }
-  val abits = io.wide.req_cmd.bits.toBits.getWidth
-  val dbits = io.wide.req_data.bits.toBits.getWidth
+  val abits = io.wide.req_cmd.bits.asUInt.getWidth
+  val dbits = io.wide.req_data.bits.asUInt.getWidth
   val rbits = io.wide.resp.bits.getWidth
 
   val out_buf = Reg(Bits())
@@ -85,10 +85,10 @@ class MemSerdes(w: Int)(implicit p: Parameters) extends MIFModule
     out_buf := out_buf >> UInt(w)
   }
   when (io.wide.req_cmd.valid && io.wide.req_cmd.ready) {
-    out_buf := io.wide.req_cmd.bits.toBits
+    out_buf := io.wide.req_cmd.bits.asUInt
   }
   when (io.wide.req_data.valid && io.wide.req_data.ready) {
-    out_buf := io.wide.req_data.bits.toBits
+    out_buf := io.wide.req_data.bits.asUInt
   }
 
   io.wide.req_cmd.ready := state === s_idle
@@ -143,8 +143,8 @@ class MemDesserIO(w: Int)(implicit p: Parameters) extends ParameterizedBundle()(
 class MemDesser(w: Int)(implicit p: Parameters) extends Module // test rig side
 {
   val io = new MemDesserIO(w)
-  val abits = io.wide.req_cmd.bits.toBits.getWidth
-  val dbits = io.wide.req_data.bits.toBits.getWidth
+  val abits = io.wide.req_cmd.bits.asUInt.getWidth
+  val dbits = io.wide.req_data.bits.asUInt.getWidth
   val rbits = io.wide.resp.bits.getWidth
   val mifDataBeats = p(MIFDataBeats)
 
@@ -203,7 +203,7 @@ class MemDesser(w: Int)(implicit p: Parameters) extends Module // test rig side
   dataq.io.deq.ready := recv_cnt === UInt((rbits-1)/w)
 
   io.narrow.resp.valid := dataq.io.deq.valid
-  io.narrow.resp.bits := dataq.io.deq.bits.toBits >> (recv_cnt * UInt(w))
+  io.narrow.resp.bits := dataq.io.deq.bits.asUInt >> (recv_cnt * UInt(w))
 }
 
 class MemIOArbiter(val arbN: Int)(implicit p: Parameters) extends MIFModule {
@@ -239,7 +239,7 @@ class MemIOArbiter(val arbN: Int)(implicit p: Parameters) extends MIFModule {
     io.outer.resp.ready := Bool(false)
     for (i <- 0 until arbN) {
       io.inner(i).resp.valid := Bool(false)
-      when(io.outer.resp.bits.tag(log2Up(arbN)-1,0).toUInt === UInt(i)) {
+      when(io.outer.resp.bits.tag(log2Up(arbN)-1,0) === UInt(i)) {
         io.inner(i).resp.valid := io.outer.resp.valid
         io.outer.resp.ready := io.inner(i).resp.ready
       }

junctions/src/main/scala/slowio.scala

@@ -21,8 +21,8 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
   val hold = Reg(init=UInt(divisor_max/4-1))
   val h_shadow = Reg(init=UInt(divisor_max/4-1))
   when (io.set_divisor.valid) {
-    d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0).toUInt
-    h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16).toUInt
+    d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0)
+    h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16)
   }
   io.divisor := (hold << 16) | divisor
 

junctions/src/main/scala/smi.scala

@@ -128,7 +128,7 @@ class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
   io.nasti.r.valid := (state === s_resp)
   io.nasti.r.bits := NastiReadDataChannel(
     id = id,
-    data = buffer.toBits,
+    data = buffer.asUInt,
     last = (nBeats === UInt(0)))
 
   when (io.nasti.ar.fire()) {
@@ -192,7 +192,7 @@ class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
   def makeStrobe(offset: UInt, size: UInt, strb: UInt) = {
     val sizemask = (UInt(1) << (UInt(1) << size)) - UInt(1)
     val bytemask = strb & (sizemask << offset)
-    Vec.tabulate(maxWordsPerBeat){i => bytemask(dataBytes * i)}.toBits
+    Vec.tabulate(maxWordsPerBeat){i => bytemask(dataBytes * i)}.asUInt
   }
 
   val size = Reg(UInt(width = nastiXSizeBits))

junctions/src/main/scala/stream.scala

@@ -139,7 +139,7 @@ class StreamExpander(win: Int, wout: Int) extends Module {
 
   io.in.ready := collecting
   io.out.valid := !collecting
-  io.out.bits.data := buffer.toBits
+  io.out.bits.data := buffer.asUInt
   io.out.bits.last := last
 }
 
@@ -161,7 +161,7 @@ class Serializer[T <: Data with Serializable](w: Int, typ: T) extends Module {
   }
 
   val narrower = Module(new StreamNarrower(typ.nbits, w))
-  narrower.io.in.bits.data := io.in.bits.toBits
+  narrower.io.in.bits.data := io.in.bits.asUInt
   narrower.io.in.bits.last := Bool(true)
   narrower.io.in.valid := io.in.valid
   io.in.ready := narrower.io.in.ready