riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
1,054 Commits 1 Branch 0 Tags
0ff4fd0ccdfa4fc345dfc32a266117a66b57697b
Commit Graph

1045 Commits

Author SHA1 Message Date
Andrew Waterman c8c312e860 minor btb cleanup 2015-07-29 15:03:01 -07:00
Andrew Waterman a2fdcdcaef Use Seq, not Iterable, when traversal order matters 2015-07-29 00:24:58 -07:00
Andrew Waterman 431dd2219b Another Bits -> BitPat 2015-07-28 20:13:56 -07:00
Andrew Waterman 049fc8dc24 Chisel3 compatibility: use BitPat for don't-cares 
This one's hella ugly, but for the time being, idgaf.
 2015-07-28 02:48:49 -07:00
Andrew Waterman f2dcc40e67 Chisel3 compatibility changes 2015-07-27 12:42:20 -07:00
Andrew Waterman ae73e3a997 Only instantiate div/sqrt unit if requested 2015-07-22 22:18:18 -07:00
Andrew Waterman e9433ee01e Minor cleanup 2015-07-22 17:38:08 -07:00
Andrew Waterman b4e4ceed3d Factor out some more hazard detection code 2015-07-22 15:52:13 -07:00
Andrew Waterman bd785e7d19 Factor out common hazard detection code 2015-07-22 15:46:20 -07:00
Andrew Waterman cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) 2015-07-21 17:10:56 -07:00
Andrew Waterman ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman 5b7f3c3006 Don't use clone 2015-07-15 17:30:50 -07:00
Henry Cook f5b3649b73 Merge commit 'd819fb28c3370747475d7c5f4b641723cab1fd0c' into rocc-fpu-port 2015-07-15 15:29:56 -07:00
Andrew Waterman be2ff6dec7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:33:46 -07:00
Andrew Waterman a78e28523c Chisel3: Don't mix Mux types 2015-07-11 14:06:08 -07:00
Andrew Waterman 3233867390 Use Chisel3 SeqMem construct 2015-07-11 13:34:57 -07:00
Henry Cook 5ed2899e56 Merge pull request #10 from wsong83/fix 
L1 D$ writeback unit, reduce re-read data array
 2015-07-06 15:18:49 -07:00
Andrew Waterman 5362e2bbbd New machine-mode timer facility 2015-07-05 16:38:49 -07:00
Andrew Waterman 5e009ecc75 Fix an apparently benign PC sign-extension bug 2015-06-11 16:08:39 -07:00
Colin Schmidt 4b6cd7f3eb Merge branch 'master' of ucb-bar/rocket into rocc-fpu-port for priv1.7 2015-06-03 15:51:53 -07:00
Wei Song 4db60d9e9d code clean in dcache, no need to check the condition twice. 2015-06-02 22:06:12 +01:00
Wei Song b6e68773fd nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array. 2015-05-30 16:25:27 +01:00
Andrew Waterman 6a9390c50e Avoid spurious D$ assertion failures 
For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
 2015-05-19 03:00:53 -07:00
Andrew Waterman f460cb6c54 Update to privileged architecture 1.7 2015-05-19 02:32:21 -07:00
Andrew Waterman 254498042a Fix Split for 0-width wires 2015-05-18 18:23:17 -07:00
Andrew Waterman d31b26c342 Clean up handling of icache's io.cpu.npc signal 2015-05-18 18:22:48 -07:00
Christopher Celio b09832f1b5 ICache now returns the "next PC" signal. 
useful for other modules that need access to the fetch PC on the
   cycle it is sent to the SRAM.
 2015-05-07 04:53:05 -07:00
Colin Schmidt c746ef8702 fix bug in rocc port resp for FPtoInt instructions 2015-05-04 11:20:55 -07:00
Yunsup Lee b9fb1bb46e Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-04-29 00:43:53 -07:00
Colin Schmidt a37fad2e9b Merge branch 'retimeable-frontend' into rocc-fpu-port 2015-04-22 14:23:52 -07:00
Colin Schmidt 1f410ac42c move fetch buffer into frontend to allow retiming 2015-04-22 11:26:03 -07:00
Henry Cook a315fe93c1 simplify ClientMetadata.makeRelease 2015-04-20 10:46:24 -07:00
Albert Ou ca5b3d988d Merge branch 'master' into rocc-fpu-port 2015-04-19 15:00:00 -07:00
Henry Cook 3048f4785a HeaderlessTileLinkIO -> ClientTileLinkIO 2015-04-17 16:56:53 -07:00
Colin Schmidt 73fa28521d Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port 2015-04-16 15:22:08 -07:00
Henry Cook 49f1c0aa7b moved ecc lib to uncore 2015-04-13 15:58:10 -07:00
Henry Cook 91e882e3f8 Use HeaderlessTileLinkIO 2015-04-13 15:58:10 -07:00
Christopher Celio 517d0d4b89 feedback on PR 2015-04-12 18:44:03 -07:00
Christopher Celio 4d6ebded02 Added assert to nbdcache 2015-04-11 02:58:34 -07:00
Christopher Celio a564f08702 Rename dmem.sret signal to more accurate invalidate_lr 2015-04-11 02:26:33 -07:00
Christopher Celio 8fc2d38ca9 Removed unnecessary signal in CSRIO 2015-04-11 02:20:34 -07:00
Christopher Celio 2f88c5ca9d Renamed PCR to CSR 2015-04-11 02:16:44 -07:00
Christopher Celio 11dbd4221a Fixed front-end to support four-wide fetch. 2015-04-10 17:53:47 -07:00
Colin Schmidt bd72db92c1 update rocc port to use fdiv/sqrt 2015-04-07 15:02:02 -07:00
Colin Schmidt 887a8de189 Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port 2015-04-06 13:48:44 -07:00
Andrew Waterman 9ade0e41cc Integrate divide/sqrt unit 2015-04-04 16:39:17 -07:00
Andrew Waterman fe27b9b1b2 Support writing sstatus.fs even without an FPU 2015-04-04 15:20:18 -07:00
Andrew Waterman bce62d5774 Update PTE format to reflect reserved bits 2015-04-04 15:19:15 -07:00
Colin Schmidt a369d8f17f Add fpu port to the rocc interface 2015-04-02 01:30:11 -07:00
Andrew Waterman d912ea265e New virtual memory implementation (Sv39) 2015-03-27 16:20:59 -07:00