0ff4fd0ccd
Fix IOMSHR to send finishes for stores
2016-04-30 22:20:29 -07:00
491184a8f8
ERET -> xRET; remove mcfgaddr
2016-04-30 17:32:51 -07:00
5af98145b9
don't signal bad physical address on TLB miss
2016-04-30 17:31:46 -07:00
cae4265f3b
Change mcfgaddr pointer
2016-04-28 16:14:05 -07:00
739cf07637
Remove mtime/mtimecmp
...
The RTC is now a device that lives on the MMIO bus.
2016-04-27 14:54:51 -07:00
fb5c38c186
Handle invalidate_lr in cache arbiter, not tile
2016-04-27 11:22:04 -07:00
b99db83e67
Avoid needless Vec generation
2016-04-27 00:28:39 -07:00
8acec8eb36
Remove dead code from BTB
2016-04-27 00:28:12 -07:00
fe8c91f620
Fix IOMSHR state machine bug
...
Sending the finish too early causes the CPU response to get dropped.
attn @zhemao
2016-04-26 15:32:25 -07:00
5fd5b58743
Remove stats CSR
2016-04-26 15:31:32 -07:00
d93677a343
Support larger cache sets when not using VM
2016-04-26 15:31:32 -07:00
5dbf9640e2
Use TLB flush signal to I$ explicitly
2016-04-22 15:41:31 -07:00
84fd45fd77
Pass TLB flush signal to I$ explicitly
2016-04-22 15:20:17 -07:00
b7527268bb
use address map instead of MMIOBase to find size of memory
2016-04-21 18:44:39 -07:00
2d6f35525e
Added Field[Int] to SFMALatency/DFMALatency params
2016-04-06 14:50:57 -07:00
51e0870e23
Separate I$ and D$ interface signals that span clock cycles
...
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
dc662f28a0
Specify width on s1_pc to avoid width inference problem
2016-04-01 17:28:42 -07:00
72f7f71eb5
No need to allow finishes to be sent in s_refill_resp state
...
This is a hold-over from when writebacks needed finish messages.
2016-04-01 16:19:57 -07:00
78bc18736e
LRSC startvation fix: HellaCache generates its own Finish messages again.
2016-04-01 16:04:25 -07:00
37b9051762
No need to validate npc if BTB is disabled
2016-04-01 15:54:57 -07:00
4480d1e817
Don't compile BTB when nEntries=0
2016-04-01 15:14:45 -07:00
d406dc1231
Remove vestigial BTB enable option
2016-04-01 15:14:34 -07:00
54dd82ff76
bugfix for WB data buffer
2016-03-31 17:53:49 -07:00
1792d01ce1
fix leaky assert in nbdcache
...
Squash of #33 .
2016-03-31 15:56:14 -07:00
adb7eacf6e
Fix Chisel3 build for XLen=32
2016-03-30 22:48:51 -07:00
70664bbca0
Fix Chisel3 build for UseVM=false
2016-03-30 22:48:31 -07:00
8ad8e8a691
Add partial Sv48/Sv57 support
...
Right now, we don't support Sv39 and Sv48 at the same time, which needs
to change.
2016-03-30 11:02:22 -07:00
e652821962
Use correct kind of TileLink arbiter
...
It was "correct" before, but broke Chisel3 build.
2016-03-28 22:53:47 -07:00
5ce3527b88
Merge pull request #32 from ucb-bar/pr-btb-masking
...
separate btb response mask from the frontend mask
2016-03-26 18:15:14 -07:00
f526d380fd
separate btb response mask from the frontend mask
...
It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
2016-03-26 05:37:26 -07:00
ed280fb3de
Remove empty when statement (???)
2016-03-25 15:52:18 -07:00
1ae6d09751
Slightly ameliorate D$->I$ critical path via scoreboard
2016-03-25 15:29:32 -07:00
a4685a073f
Don't instantiate PTW when UseVM=false
2016-03-25 14:17:25 -07:00
27b3cca046
Discover D$, PTW port counts dynamically
...
This is a generator, after all...
2016-03-25 14:16:56 -07:00
8d1ba4d1ec
Remove hard-coded XLEN values from D$
2016-03-24 14:52:12 -07:00
7ae44d4905
Add RV32 support
2016-03-10 17:32:00 -08:00
82c595d11a
Fix no-FPU elaboration of CSR file
2016-03-10 17:30:56 -08:00
bc15e8649e
WIP on priv spec v1.9
2016-03-02 23:29:58 -08:00
091782ad27
Merge pull request #29 from ucb-bar/rocc-ptw-refactoring
...
RoCC PTW refactoring
2016-02-25 17:57:22 -08:00
15ac4d317f
RoCC PTW refactoring
2016-02-25 17:15:38 -08:00
b96343a4e5
[btb] fix mix type error for fetch-width > 1
...
closes #24
2016-02-08 17:41:38 -08:00
31dd311aff
[fpu] fix rounding mode bug in fdivfsqrt
2016-02-08 17:38:31 -08:00
5abfd1a4ab
make sure to check for region violations in DMA frontend
2016-02-03 15:40:44 -08:00
78579672d3
make mtvec configurable and writeable
2016-01-29 14:51:56 -08:00
7937fbf074
fix number of IOMSHRs at 1
2016-01-29 14:51:56 -08:00
305185c034
send DMA requests through MMIO and get responses through CSRs
2016-01-29 14:51:56 -08:00
58fcc6b7c6
Get rid of useless mux
2016-01-28 11:44:59 -08:00
d170fcd913
DecoupledHelper is now imported from junctions
2016-01-21 15:38:43 -08:00
52d6b0b1a5
Improve ALU QoR
...
Rejigger muxes; share XOR gates between ADD/SUB, XOR, and BEQ.
2016-01-20 17:42:31 -08:00
77e068c153
fix Chisel3 compat issue in SimpleHellaCacheIF
2016-01-14 22:42:44 -08:00
