make sure to check for region violations in DMA frontend
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78579672d3
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5abfd1a4ab
@ -53,7 +53,7 @@ object ClientDmaRequest {
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object ClientDmaResponse {
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val pagefault = UInt("b01")
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val outer_err = UInt("b10")
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val invalid_region = UInt("b10")
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def apply(status: UInt = UInt(0))(implicit p: Parameters) = {
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val resp = Wire(new ClientDmaResponse)
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@ -164,6 +164,12 @@ class DmaFrontend(implicit p: Parameters) extends CoreModule()(p)
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alloc = Bool(false))
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}
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def check_region(cmd: UInt, src: UInt, dst: UInt): Bool = {
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val dst_ok = Mux(cmd === DMA_CMD_SOUT, dst >= UInt(mmioBase), dst < UInt(mmioBase))
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val src_ok = Mux(cmd === DMA_CMD_SIN, src >= UInt(mmioBase), Bool(true))
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dst_ok && src_ok
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}
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tlb.io.req.valid := tlb_to_send.orR
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tlb.io.req.bits.vpn := Mux(tlb_to_send(0), src_vpn, dst_vpn)
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tlb.io.req.bits.passthrough := Bool(false)
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@ -227,7 +233,12 @@ class DmaFrontend(implicit p: Parameters) extends CoreModule()(p)
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}
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when (state === s_translate && !to_translate.orR) {
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state := s_dma_req
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when (check_region(cmd, src_paddr, dst_paddr)) {
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state := s_dma_req
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} .otherwise {
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resp_status := ClientDmaResponse.invalid_region
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state := s_finish
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}
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}
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def setBusy(set: Bool, xact_id: UInt): UInt =
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