riscv/rocket-chip
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  • a87c2d13e2 tilelink2: include an abstract definition for register mapped devices Wesley W. Terpstra 2016-08-26 14:15:37 -0700
  • 3a441d853f tilelink2: clarify that fifoId only applies to accesses (not hints) Wesley W. Terpstra 2016-08-26 14:13:54 -0700
  • 4b99bd3be1 tilelink2: mask out unnecessary address bits Wesley W. Terpstra 2016-08-26 14:13:09 -0700
  • e24ba61754 tilelink2: distinguish two levels of uncacheability Wesley W. Terpstra 2016-08-24 16:07:45 -0700
  • e506309998 tilelink2: prototype crossbar implementation Wesley W. Terpstra 2016-08-24 13:50:32 -0700
  • 34f65938b6 tilelink2: add a TLBundle constructor Wesley W. Terpstra 2016-08-24 13:50:11 -0700
  • 1cd85ff050 tilelink2: add some bundle introspection to scaffold the xbar Wesley W. Terpstra 2016-08-23 16:23:35 -0700
  • 9c62f5d9c1 tilelink2: shave off a few more firrtl monitor lines Wesley W. Terpstra 2016-08-22 16:43:00 -0700
  • af29595979 tilelink2: eliminate common subexpressions in Monitor to reduce firrtl output Wesley W. Terpstra 2016-08-22 16:03:26 -0700
  • d7e839280f tilelink2: include legal message monitor Wesley W. Terpstra 2016-08-22 15:37:30 -0700
  • 492a38aedc tilelink2: only accesses can have errors (release must make forward progress) Wesley W. Terpstra 2016-08-22 15:36:39 -0700
  • 6599bcb77b tilelink2: statically check Operations are remotely plausible Wesley W. Terpstra 2016-08-22 13:28:52 -0700
  • 8cff45f254 tilelink2: use byte-aligned addressing Wesley W. Terpstra 2016-08-22 13:18:01 -0700
  • 45e152e97e tilelink2: include Operation constructors Wesley W. Terpstra 2016-08-19 20:28:58 -0700
  • 5b10c1a328 tilelink2: arithmetic and logical atomics must be distinct (priv spec 3.5.3) Wesley W. Terpstra 2016-08-19 18:39:21 -0700
  • 8592cbf0e3 tilelink2: Message and Permisison types from Henry Wesley W. Terpstra 2016-08-19 15:25:51 -0700
  • 9a460322da tilelink2: add synthesizable test methods for Parameters Wesley W. Terpstra 2016-08-19 13:47:18 -0700
  • 7328b55abd tilelink2: first cut at parameterization Wesley W. Terpstra 2016-08-19 11:08:35 -0700
  • 59a2e6a4dc Merge pull request #244 from ucb-bar/compelete-dramsim-removal Howard Mao 2016-09-05 15:05:38 -0700
  • ba4b3e14cc remove remaining dramsim2 files Colin Schmidt 2016-09-04 17:25:24 -0700
  • 8906097250 have Travis cache the entire verilator directory Howard Mao 2016-09-04 15:05:30 -0700
  • a7f79aa409 get rid of TileLinkMemorySelector Howard Mao 2016-09-03 21:14:04 -0700
  • f0ab6d0214 tie off finish signals in tilelink wrapper and unwrapper Howard Mao 2016-09-03 20:43:11 -0700
  • 66de89c4db allow fixed priority routing in Junctions arbiters Howard Mao 2016-09-03 20:42:47 -0700
  • efe8670283 allow Serializer/Deserializer to work with arbitrary Chisel data types Howard Mao 2016-09-03 20:41:48 -0700
  • b9b79e4fb6 get rid of AtoS RTL Howard Mao 2016-09-03 20:41:04 -0700
  • f34843f1b9 fix assignment of incoherent vector Howard Mao 2016-09-03 21:55:09 -0700
  • a4c1942958 flatten Coreplex module hierarchy Yunsup Lee 2016-09-02 17:45:08 -0700
  • 63679bb019 Add support for L1 data scratchpads instead of caches Andrew Waterman 2016-09-02 15:59:16 -0700
  • dc9ae19936 Work-around for current Scala compiler "structural type loses implicits". Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler. Jim Lawson 2016-08-23 10:54:19 -0700
  • fb50f7c9dd Set default TileLink width to XLen Andrew Waterman 2016-09-02 14:56:00 -0700
  • e23e4d6de5 Add ClientUncachedTileLinkEnqueuer utility Andrew Waterman 2016-09-02 14:53:42 -0700
  • 7aeb42fa55 Allow narrow TL interface on PRCI; make mtime writable Andrew Waterman 2016-09-02 14:48:16 -0700
  • 6872000f5e Merge pull request #239 from ucb-bar/move_rtc Andrew Waterman 2016-09-02 15:17:49 -0700
  • af364bc7bc Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal Megan Wachs 2016-09-02 15:14:39 -0700
  • 8163a6b597 Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications Megan Wachs 2016-09-02 11:11:40 -0700
  • c05ba1e864 Add TileId parameter, generalizing GroundTestId Andrew Waterman 2016-09-02 00:05:40 -0700
  • 4a7972be31 connect testharness components via member functions (#236) Yunsup Lee 2016-09-01 18:38:39 -0700
  • 08089f695d allow configuration to be in separate project from test harness Howard Mao 2016-09-01 10:28:07 -0700
  • c66318307c no longer need to set invalidate_lr in RoCC examples Howard Mao 2016-08-31 22:05:35 -0700
  • 27c674972c tie off invalidate_lr in RoCC Howard Mao 2016-08-31 09:44:32 -0700
  • bb578494d8 don't override req.bits.phys in SimpleHellaCacheIF Howard Mao 2016-08-31 09:44:16 -0700
  • 50d6738caf make sure DummyPTW sets all the necessary status and ptbr signals Howard Mao 2016-08-30 14:43:00 -0700
  • 403cc1c5c4 fix DecoupledTLB to handle misses appropriately Howard Mao 2016-08-23 18:36:03 -0700
  • f4524e4c91 Add PML for Boolean.option; use it Andrew Waterman 2016-08-29 15:56:28 -0700
  • 2dfcf18167 Filter simv command-line args starting with -cm Andrew Waterman 2016-08-30 16:49:39 -0700
  • cf1bd90a70 Merge pull request #234 from zizztux/fix_export_mmio Howard Mao 2016-08-30 15:58:01 -0700
  • b1ce3b8c98 Add address map entries for exported mmio port. SeungRyeol Lee 2016-08-31 06:58:38 +0900
  • 8dbee2b133 Don't conditionalize running bmarks on UseVM Andrew Waterman 2016-08-29 13:43:29 -0700
  • 07d48df88a Get rid of FPU RoCC port logic when RoCC not present Andrew Waterman 2016-08-17 18:23:25 -0700
  • f91552a650 Add performance counter support Andrew Waterman 2016-08-26 20:27:27 -0700
  • 1e3339e97c Update breakpoints to match @timsifive's debug spec Andrew Waterman 2016-08-25 23:07:34 -0700
  • 9ca82dd397 reset default MulDiv config to moderately fast default Andrew Waterman 2016-08-25 19:31:18 -0700
  • 33eaf08b60 set missing port direction Andrew Waterman 2016-08-25 19:33:03 -0700
  • a19bd6de96 Get in line with FIRRTL randomization flag changes (#231) Howard Mao 2016-08-29 12:29:01 -0700
  • 35948918b6 Merge pull request #226 from ucb-bar/coreplex_peripheral_interrupts mwachs5 2016-08-26 11:52:04 -0700
  • 53ee54dbd1 Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself Megan Wachs 2016-08-26 10:09:03 -0700
  • 41aa80c5d7 Merge remote-tracking branch 'origin/master' into coreplex_peripheral_interrupts Megan Wachs 2016-08-26 09:32:36 -0700
  • 79293f4fa2 Use a better iterator inside the DCache Ben Keller 2016-08-25 15:49:44 -0700
  • 115e8edd83 Merge branch 'master' into coreplex_peripheral_interrupts Henry Cook 2016-08-25 17:26:56 -0700
  • 93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) Henry Cook 2016-08-25 17:26:28 -0700
  • abfaae8f4b Merge branch 'master' into coreplex_peripheral_interrupts Henry Cook 2016-08-25 14:57:53 -0700
  • 4f388add67 More accurate conditional include of generated .d make fragment (#222) Ben Keller 2016-08-25 14:42:04 -0700
  • 428eed79a1 Allow some External Interrupts to come from Periphery Megan Wachs 2016-08-25 10:04:31 -0700
  • 8ff739d3fa Merge pull request #225 from ucb-bar/remove-openocd mwachs5 2016-08-25 11:01:17 -0700
  • 3a674b413d Remove openocd from .gitmodules Megan Wachs 2016-08-25 10:05:30 -0700
  • d5d076200e Merge pull request #213 from ucb-bar/new_test_jtag_DTM mwachs5 2016-08-23 18:18:18 -0700
  • 67467c65f5 Add a jtag-dtm-regression target to the regression Megan Wachs 2016-08-23 16:53:50 -0700
  • 32118269c1 Remove } introduced in merge Megan Wachs 2016-08-23 08:20:52 -0700
  • c22c77c7a4 remove pointer to openOCD Megan Wachs 2016-08-23 07:35:48 -0700
  • 9974626d6a Merge remote-tracking branch 'origin/master' into HEAD Megan Wachs 2016-08-23 07:34:01 -0700
  • 61aa716f44 fix bus axi connections in periphery Howard Mao 2016-08-19 18:57:34 -0700
  • f9ea14b4c2 extra devices should get elaborated in a single build function Howard Mao 2016-08-19 18:26:34 -0700
  • 96e2cefb34 Merge branch 'master' into HEAD Scott Johnson 2016-08-22 11:37:30 -0700
  • 8d6f080ed0 Merge pull request #215 from ucb-bar/test-harness-fixes Scott Johnson 2016-08-22 10:33:01 -0700
  • b7181ba49b Merge branch 'master' into test-harness-fixes Andrew Waterman 2016-08-19 22:53:12 -0700
  • 22ffe36258 Add a queue for timing QoR between L2->MMIO network (#217) mwachs5 2016-08-19 22:51:49 -0700
  • 96a868d388 enable the TestDriver to be used in a SystemVerilog UVM-based testbench, which has its own way to manage end-of-simulation and does not like anyone else to call $finish Scott Johnson 2016-08-19 17:14:54 -0700
  • 2d12f6689c make CLOCK_PERIOD actually be the clock period, instead of half of the clock period Scott Johnson 2016-08-19 14:44:48 -0700
  • 4dbcc568dc reorder code to get rid of messy -1 Scott Johnson 2016-08-12 17:03:21 -0700
  • f945acf712 rm race condition on trace_count Scott Johnson 2016-08-12 16:58:22 -0700
  • 75efc7dee7 JtagIO's DRV_TDO should be an INPUT Megan Wachs 2016-08-19 16:38:03 -0700
  • 723cc063cb Move files after the file reorganization Megan Wachs 2016-08-19 16:11:41 -0700
  • 48c5ec3551 add missing jtag file Megan Wachs 2016-08-19 15:28:53 -0700
  • 66a253a0db Remove unncessary file Megan Wachs 2016-08-19 14:18:51 -0700
  • 3dd51ff734 This commit adds Logic & test support for JTAG implementation of Debug Transport Module. Megan Wachs 2016-08-19 14:01:33 -0700
  • dd4a50c452 Add JTAG DTM and test support in simulation Megan Wachs 2016-08-19 09:46:43 -0700
  • ceff6dd0c8 update README Howard Mao 2016-08-19 11:39:30 -0700
  • 40bd87bce4 cache the verilator install in travis Howard Mao 2016-08-19 11:13:24 -0700
  • 1c5034707b fix submodules in regression makefile Howard Mao 2016-08-19 11:10:20 -0700
  • f4e0e0966c move rocketchip package sources into its own subdirectory Howard Mao 2016-08-19 11:08:38 -0700
  • eba692786b make sure FIRRTL jar gets updated timestamp Howard Mao 2016-08-19 11:06:01 -0700
  • 7b20609d4d reorganize moving non-submodule packages into src/main/scala Howard Mao 2016-08-19 10:58:56 -0700
  • f78da0b0ea add required cloneType methods in non-blocking L1 Howard Mao 2016-08-19 13:44:53 -0700
  • 114226252b Hierarchicalize D$ config Andrew Waterman 2016-08-17 16:53:39 -0700
  • 3f8c60bbd6 Hierarchicalize FPU and MulDiv parameters Andrew Waterman 2016-08-17 00:57:35 -0700
  • fee5d2b1ea Remove parameters for some things that aren't parameterizable Andrew Waterman 2016-08-16 20:04:02 -0700
  • 33676e81f8 use isOneOf as much as possible Howard Mao 2016-08-19 09:46:43 -0700
  • d34e790ac0 get rid of duplicated code in rocket Util Howard Mao 2016-08-18 18:40:07 -0700
  • 7671811ac9 merge uncore.Util into uncore.util Howard Mao 2016-08-18 18:33:46 -0700