Merge pull request #215 from ucb-bar/test-harness-fixes
Test harness fixes
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commit
8d6f080ed0
@ -39,7 +39,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
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$(RISCV)/lib/libfesvr.so \
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-sverilog \
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+incdir+$(generated_dir) \
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+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
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+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+STOP_COND=!$(TB).reset \
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+define+RANDOMIZE \
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@ -5,7 +5,7 @@ module TestDriver;
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reg clk = 1'b0;
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reg reset = 1'b1;
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always #`CLOCK_PERIOD clk = ~clk;
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always #(`CLOCK_PERIOD/2.0) clk = ~clk;
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initial #777.7 reset = 0;
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// Read input arguments and initialize
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@ -39,12 +39,25 @@ module TestDriver;
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`endif
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end
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`ifdef TESTBENCH_IN_UVM
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// UVM library has its own way to manage end-of-simulation.
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// A UVM-based testbench will raise an objection, watch this signal until this goes 1, then drop the objection.
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reg finish_request = 1'b0;
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`endif
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reg [255:0] reason = "";
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reg failure = 1'b0;
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wire success;
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integer stderr = 32'h80000002;
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always @(posedge clk)
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begin
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`ifdef GATE_LEVEL
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if (verbose)
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begin
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$fdisplay(stderr, "C: %10d", trace_count);
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end
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`endif
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trace_count = trace_count + 1;
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if (!reset)
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begin
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if (max_cycles > 0 && trace_count > max_cycles)
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@ -65,22 +78,15 @@ module TestDriver;
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if (verbose)
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$fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
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`VCDPLUSCLOSE
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`ifdef TESTBENCH_IN_UVM
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finish_request = 1;
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`else
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$finish;
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`endif
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end
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end
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end
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always @(posedge clk)
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begin
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trace_count = trace_count + 1;
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`ifdef GATE_LEVEL
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if (verbose)
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begin
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$fdisplay(stderr, "C: %10d", trace_count-1);
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end
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`endif
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end
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TestHarness testHarness(
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.clk(clk),
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.reset(reset),
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