riscv/rocket-chip
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Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal

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This commit is contained in:
Megan Wachs 2016-09-02 15:14:39 -07:00
parent 8163a6b597
commit af364bc7bc
2 changed files with 4 additions and 3 deletions
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2
src/main/scala/rocketchip/Configs.scala
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@ -154,7 +154,7 @@ class BasePlatformConfig extends Config (
case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case RTC => (p: Parameters, t_io: Bundle, p_io:Bundle) => Counter(p(RTCPeriod)).inc()
case RTCTick => (p: Parameters, t_io: Bundle, p_io:Bundle) => Counter(p(RTCPeriod)).inc()
case _ => throw new CDEMatchError
}})

5
src/main/scala/rocketchip/RocketChip.scala
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@ -54,7 +54,7 @@ case object ExtMemSize extends Field[Long]
case object NExtTopInterrupts extends Field[Int]
case object NExtPeripheryInterrupts extends Field[Int]
/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
case object RTC extends Field[(Parameters, Bundle, Bundle) => Bool]
case object RTCTick extends Field[(Parameters, Bundle, Bundle) => Bool]
case object RTCPeriod extends Field[Int]
@ -199,12 +199,13 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
io.extra <> periphery.io.extra
coreplex.io.rtcTick := p(RTC)(p, io.extra, periphery.io.extra)
coreplex.io.rtcTick := p(RTCTick)(p, io.extra, periphery.io.extra)
p(ConnectExtraPorts)(io.extra, coreplex.io.extra, p)
}
class Periphery(implicit val p: Parameters) extends Module
with HasTopLevelParameters {
val io = new Bundle {