riscv/rocket-chip
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Don't conditionalize running bmarks on UseVM

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This commit is contained in:
Andrew Waterman
2016-08-29 13:43:29 -07:00
parent 07d48df88a
commit 8dbee2b133
2 changed files with 2 additions and 2 deletions
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2
riscv-tools

Submodule riscv-tools updated: 9533264227...705db10fd1

2
src/main/scala/coreplex/Configs.scala
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@ -93,7 +93,7 @@ class BaseCoreplexConfig extends Config (
else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)
TestGeneration.addSuite(benchmarks)
List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
Module(new RocketTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2"