Merge pull request #244 from ucb-bar/compelete-dramsim-removal

remove remaining dramsim2 files

emulator/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini

@@ -1,58 +0,0 @@
-NUM_BANKS=8
-NUM_ROWS=32768
-NUM_COLS=2048
-DEVICE_WIDTH=4
-
-;in nanoseconds
-;#define REFRESH_PERIOD 7800
-REFRESH_PERIOD=7800
-tCK=1.5 ;*
-
-CL=10 ;*
-AL=0 ;*
-;AL=3; needs to be tRCD-1 or 0
-;RL=(CL+AL)
-;WL=(RL-1)
-BL=8 ;*
-tRAS=24;* 
-tRCD=10 ;*
-tRRD=4 ;*
-tRC=34 ;*
-tRP=10  ;*
-tCCD=4 ;*
-tRTP=5 ;*
-tWTR=5 ;*
-tWR=10 ;*
-tRTRS=1; -- RANK PARAMETER, TODO 
-tRFC=107;*
-tFAW=20;*
-tCKE=4 ;*
-tXP=4 ;*
-
-tCMD=1 ;*
-
-IDD0=100;
-IDD1=130;
-IDD2P=10;
-IDD2Q=70;
-IDD2N=70;
-IDD3Pf=60;
-IDD3Ps=60;
-IDD3N=90;
-IDD4W=255;
-IDD4R=230;
-IDD5=305;
-IDD6=9;
-IDD6L=12;
-IDD7=415;
-
-;same bank
-;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2)
-;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR)
-;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL)
-;READ_AUTOPRE_DELAY=(AL+tRTP+tRP)
-;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP)
-;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
-;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
-
-Vdd=1.5 ; TODO: double check this

emulator/dramsim2_ini/system.ini

@@ -1,25 +0,0 @@
-; COPY THIS FILE AND MODIFY IT TO SUIT YOUR NEEDS
-
-NUM_CHANS=1								; number of *logically independent* channels (i.e. each with a separate memory controller); should be a power of 2
-JEDEC_DATA_BUS_BITS=64 		 		; Always 64 for DDRx; if you want multiple *ganged* channels, set this to N*64
-TRANS_QUEUE_DEPTH=32					; transaction queue, i.e., CPU-level commands such as:  READ 0xbeef
-CMD_QUEUE_DEPTH=32						; command queue, i.e., DRAM-level commands such as: CAS 544, RAS 4
-EPOCH_LENGTH=100000						; length of an epoch in cycles (granularity of simulation)
-ROW_BUFFER_POLICY=open_page 		; close_page or open_page
-ADDRESS_MAPPING_SCHEME=scheme2	;valid schemes 1-7; For multiple independent channels, use scheme7 since it has the most parallelism 
-SCHEDULING_POLICY=rank_then_bank_round_robin  ; bank_then_rank_round_robin or rank_then_bank_round_robin 
-QUEUING_STRUCTURE=per_rank			;per_rank or per_rank_per_bank
-
-;for true/false, please use all lowercase
-DEBUG_TRANS_Q=false
-DEBUG_CMD_Q=false
-DEBUG_ADDR_MAP=false
-DEBUG_BUS=false
-DEBUG_BANKSTATE=false
-DEBUG_BANKS=false
-DEBUG_POWER=false
-VIS_FILE_OUTPUT=false
-
-USE_LOW_POWER=true 					; go into low power mode when idle?
-VERIFICATION_OUTPUT=false 			; should be false for normal operation
-TOTAL_ROW_ACCESSES=4	; 				maximum number of open page requests to send to the same row before forcing a row close (to prevent starvation)