Update breakpoints to match @timsifive's debug spec
This commit is contained in:
Andrew Waterman
parent
9ca82dd397
commit
1e3339e97c
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@ -4,79 +4,80 @@ package rocket
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import Chisel._
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import Util._
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import uncore.util._
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import cde.Parameters
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class TDRSelect(implicit p: Parameters) extends CoreBundle()(p) {
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val tdrmode = Bool()
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val reserved = UInt(width = xLen - 1 - log2Up(nTDR))
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val tdrindex = UInt(width = log2Up(nTDR))
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def nTDR = p(NBreakpoints)
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}
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class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
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val tdrtype = UInt(width = 4)
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val bpamaskmax = UInt(width = 5)
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val reserved = UInt(width = xLen-28)
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val bpaction = UInt(width = 8)
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val bpmatch = UInt(width = 4)
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val ttype = UInt(width = 4)
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val dmode = Bool()
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val maskmax = UInt(width = 6)
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val reserved = UInt(width = xLen-24)
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val action = Bool()
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val chain = Bool()
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val zero = UInt(width = 2)
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val tmatch = UInt(width = 2)
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val m = Bool()
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val h = Bool()
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val s = Bool()
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val u = Bool()
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val r = Bool()
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val w = Bool()
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val x = Bool()
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val w = Bool()
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val r = Bool()
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def tdrType = 1
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def bpaMaskMax = 4
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def enabled(mstatus: MStatus) = Cat(m, h, s, u)(mstatus.prv)
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def tType = 2
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def maskMax = 4
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def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)
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}
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class BP(implicit p: Parameters) extends CoreBundle()(p) {
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val control = new BPControl
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val address = UInt(width = vaddrBits)
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def mask(dummy: Int = 0) = {
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var mask: UInt = control.bpmatch(1)
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for (i <- 1 until control.bpaMaskMax)
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mask = Cat(mask(i-1) && address(i-1), mask)
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mask
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}
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def mask(dummy: Int = 0) =
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(0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt
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def pow2AddressMatch(x: UInt) =
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(~x | mask()) === (~address | mask())
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def rangeAddressMatch(x: UInt) =
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(x >= address) ^ control.tmatch(0)
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def addressMatch(x: UInt) =
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Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x))
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}
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class BreakpointUnit(implicit p: Parameters) extends CoreModule()(p) {
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class BreakpointUnit(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val status = new MStatus().asInput
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val bp = Vec(p(NBreakpoints), new BP).asInput
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val bp = Vec(n, new BP).asInput
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val pc = UInt(INPUT, vaddrBits)
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val ea = UInt(INPUT, vaddrBits)
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val xcpt_if = Bool(OUTPUT)
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val xcpt_ld = Bool(OUTPUT)
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val xcpt_st = Bool(OUTPUT)
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val debug_if = Bool(OUTPUT)
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val debug_ld = Bool(OUTPUT)
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val debug_st = Bool(OUTPUT)
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}
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io.xcpt_if := false
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io.xcpt_ld := false
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io.xcpt_st := false
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io.debug_if := false
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io.debug_ld := false
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io.debug_st := false
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for (bp <- io.bp) {
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when (bp.control.enabled(io.status)) {
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when (bp.pow2AddressMatch(io.pc) && bp.control.x) { io.xcpt_if := true }
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when (bp.pow2AddressMatch(io.ea) && bp.control.r) { io.xcpt_ld := true }
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when (bp.pow2AddressMatch(io.ea) && bp.control.w) { io.xcpt_st := true }
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}
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}
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io.bp.foldLeft((Bool(true), Bool(true), Bool(true))) { case ((ri, wi, xi), bp) =>
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val en = bp.control.enabled(io.status)
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val r = en && ri && bp.control.r && bp.addressMatch(io.ea)
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val w = en && wi && bp.control.w && bp.addressMatch(io.ea)
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val x = en && xi && bp.control.x && bp.addressMatch(io.pc)
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val end = !bp.control.chain
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if (!io.bp.isEmpty) for ((bpl, bph) <- io.bp zip io.bp.tail) {
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def matches(x: UInt) = !(x < bpl.address) && x < bph.address
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when (bph.control.enabled(io.status) && bph.control.bpmatch === 1) {
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when (matches(io.pc) && bph.control.x) { io.xcpt_if := true }
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when (matches(io.ea) && bph.control.r) { io.xcpt_ld := true }
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when (matches(io.ea) && bph.control.w) { io.xcpt_st := true }
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}
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when (end && r) { io.xcpt_ld := !bp.control.action; io.debug_ld := bp.control.action }
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when (end && w) { io.xcpt_st := !bp.control.action; io.debug_st := bp.control.action }
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when (end && x) { io.xcpt_if := !bp.control.action; io.debug_if := bp.control.action }
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(end || r, end || w, end || x)
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}
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}
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@ -41,7 +41,7 @@ class DCSR extends Bundle {
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val xdebugver = UInt(width = 2)
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val ndreset = Bool()
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val fullreset = Bool()
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val hwbpcount = UInt(width = 12)
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val zero3 = UInt(width = 12)
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val ebreakm = Bool()
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val ebreakh = Bool()
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val ebreaks = Bool()
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@ -101,6 +101,11 @@ object CSR
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val R = UInt(5,SZ)
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val ADDRSZ = 12
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val debugIntCause = new MIP().getWidth
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val debugTriggerCause = {
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require(debugIntCause >= Causes.all.max)
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debugIntCause
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}
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}
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class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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@ -133,7 +138,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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val rocc = new RoCCInterface().flip
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val interrupt = Bool(OUTPUT)
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val interrupt_cause = UInt(OUTPUT, xLen)
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val bp = Vec(p(NBreakpoints), new BP).asOutput
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val bp = Vec(nBreakpoints, new BP).asOutput
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}
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class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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@ -155,12 +160,12 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val (supported_interrupts, delegable_interrupts) = {
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val sup = Wire(init=new MIP().fromBits(0))
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sup.ssip := Bool(p(UseVM))
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sup.ssip := Bool(usingVM)
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sup.msip := true
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sup.stip := Bool(p(UseVM))
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sup.stip := Bool(usingVM)
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sup.mtip := true
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sup.meip := true
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sup.seip := Bool(p(UseVM))
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sup.seip := Bool(usingVM)
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sup.rocc := usingRoCC
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val del = Wire(init=sup)
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@ -189,8 +194,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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assert(!io.singleStep || io.retire <= UInt(1))
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assert(!reg_singleStepped || io.retire === UInt(0))
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val reg_tdrselect = Reg(new TDRSelect)
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val reg_bp = Reg(Vec(1 << log2Up(p(NBreakpoints)), new BP))
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val reg_tselect = Reg(UInt(width = log2Up(nBreakpoints)))
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val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
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val reg_mie = Reg(init=UInt(0, xLen))
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val reg_mideleg = Reg(init=UInt(0, xLen))
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@ -228,13 +233,12 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val interruptCause = interruptMSB + PriorityEncoder(all_interrupts)
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io.interrupt := all_interrupts.orR && !io.singleStep || reg_singleStepped
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io.interrupt_cause := interruptCause
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io.bp := reg_bp take p(NBreakpoints)
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io.bp := reg_bp take nBreakpoints
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val debugIntCause = reg_mip.getWidth
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// debug interrupts are only masked by being in debug mode
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when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {
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io.interrupt := true
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io.interrupt_cause := interruptMSB + debugIntCause
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io.interrupt_cause := interruptMSB + CSR.debugIntCause
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}
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val system_insn = io.rw.cmd === CSR.I
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@ -251,9 +255,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val read_mstatus = io.status.asUInt()(xLen-1,0)
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val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
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CSRs.tdrselect -> reg_tdrselect.asUInt,
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CSRs.tdrdata1 -> reg_bp(reg_tdrselect.tdrindex).control.asUInt,
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CSRs.tdrdata2 -> reg_bp(reg_tdrselect.tdrindex).address,
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CSRs.tselect -> reg_tselect,
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CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt,
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CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen),
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CSRs.mimpid -> UInt(0),
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CSRs.marchid -> UInt(0),
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CSRs.mvendorid -> UInt(0),
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@ -276,11 +280,14 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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CSRs.mcause -> reg_mcause,
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CSRs.mhartid -> io.prci.id)
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if (usingDebug) {
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read_mapping += CSRs.dcsr -> reg_dcsr.asUInt
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read_mapping += CSRs.dpc -> reg_dpc.asUInt
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read_mapping += CSRs.dscratch -> reg_dscratch.asUInt
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}
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val debug_csrs = collection.mutable.LinkedHashMap[Int,Bits](
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CSRs.dcsr -> reg_dcsr.asUInt,
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CSRs.dpc -> reg_dpc.asUInt,
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CSRs.dscratch -> reg_dscratch.asUInt
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)
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if (usingDebug)
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read_mapping ++= debug_csrs
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if (usingFPU) {
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read_mapping += CSRs.fflags -> reg_fflags
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@ -337,14 +344,17 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}
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val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }
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val addr_valid = decoded_addr.values.reduce(_||_)
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val fp_csr =
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if (usingFPU) decoded_addr(CSRs.fflags) || decoded_addr(CSRs.frm) || decoded_addr(CSRs.fcsr)
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else Bool(false)
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val csr_debug = Bool(usingDebug) && io.rw.addr(5)
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val csr_addr_priv = Cat(io.rw.addr(6,5).andR, io.rw.addr(9,8))
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val priv_sufficient = Cat(reg_debug, reg_mstatus.prv) >= csr_addr_priv
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val csr_addr_priv = io.rw.addr(9,8)
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val debug_csr_mask = 0x090 // only debug CSRs have address bits 7 and 4 set
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require((read_mapping -- debug_csrs.keys).keys.forall(x => (x & debug_csr_mask) != debug_csr_mask))
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require(debug_csrs.keys.forall(x => (x & debug_csr_mask) == debug_csr_mask))
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val csr_debug = Bool(usingDebug) && (io.rw.addr & debug_csr_mask) === debug_csr_mask
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val priv_sufficient = reg_debug || (!csr_debug && reg_mstatus.prv >= csr_addr_priv)
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val read_only = io.rw.addr(11,10).andR
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val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R && priv_sufficient
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val wen = cpu_wen && !read_only
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@ -374,13 +384,14 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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Mux(insn_call, reg_mstatus.prv + Causes.user_ecall,
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Mux[UInt](insn_break, Causes.breakpoint, Causes.illegal_instruction)))
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val cause_lsbs = cause(log2Up(xLen)-1,0)
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val causeIsDebugInt = cause(xLen-1) && cause_lsbs === debugIntCause
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val causeIsDebugBreak = cause === Causes.breakpoint && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
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val trapToDebug = Bool(usingDebug) && (reg_singleStepped || causeIsDebugInt || causeIsDebugBreak || reg_debug)
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val delegate = Bool(p(UseVM)) && reg_mstatus.prv < PRV.M && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs))
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val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause
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val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause
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val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
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val trapToDebug = Bool(usingDebug) && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug)
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val delegate = Bool(usingVM) && reg_mstatus.prv < PRV.M && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs))
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val debugTVec = Mux(reg_debug, UInt(0x808), UInt(0x800))
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val tvec = Mux(trapToDebug, debugTVec, Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec))
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val epc = Mux(csr_debug, reg_dpc, Mux(Bool(p(UseVM)) && !csr_addr_priv(1), reg_sepc, reg_mepc))
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val epc = Mux(csr_debug, reg_dpc, Mux(Bool(usingVM) && !csr_addr_priv(1), reg_sepc, reg_mepc))
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io.fatc := insn_sfence_vm
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io.evec := Mux(exception, tvec, epc)
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io.ptbr := reg_sptbr
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@ -403,7 +414,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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when (trapToDebug) {
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reg_debug := true
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reg_dpc := epc
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reg_dcsr.cause := Mux(reg_singleStepped, UInt(4), Mux(causeIsDebugInt, UInt(3), UInt(1)))
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reg_dcsr.cause := Mux(reg_singleStepped, 4, Mux(causeIsDebugInt, 3, Mux[UInt](causeIsDebugTrigger, 2, 1)))
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reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)
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}.elsewhen (delegate) {
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reg_sepc := epc
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@ -425,7 +436,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}
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when (insn_ret) {
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when (Bool(p(UseVM)) && !csr_addr_priv(1)) {
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when (Bool(usingVM) && !csr_addr_priv(1)) {
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when (reg_mstatus.spp.toBool) { reg_mstatus.sie := reg_mstatus.spie }
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reg_mstatus.spie := false
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reg_mstatus.spp := PRV.U
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@ -537,45 +548,48 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata & delegable_interrupts }
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when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata & delegable_exceptions }
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}
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if (p(NBreakpoints) > 0) {
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val newTDR = new TDRSelect().fromBits(wdata)
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when (decoded_addr(CSRs.tdrselect)) { reg_tdrselect.tdrindex := newTDR.tdrindex }
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if (nBreakpoints > 0) {
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when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
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when (reg_tdrselect.tdrmode || reg_debug) {
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when (decoded_addr(CSRs.tdrdata1)) {
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val bp = reg_bp(reg_tselect)
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when (!bp.control.dmode || reg_debug) {
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when (decoded_addr(CSRs.tdata1)) {
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val newBPC = new BPControl().fromBits(wdata)
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reg_bp(reg_tdrselect.tdrindex).control := newBPC
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reg_bp(reg_tdrselect.tdrindex).control.bpmatch := newBPC.bpmatch & 2 /* exact/NAPOT only */
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val dMode = newBPC.dmode && reg_debug
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bp.control := newBPC
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bp.control.dmode := dMode
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bp.control.action := dMode && newBPC.action
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}
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when (decoded_addr(CSRs.tdrdata2)) { reg_bp(reg_tdrselect.tdrindex).address := wdata }
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when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
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}
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}
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}
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reg_mip := io.prci.interrupts
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reg_dcsr.debugint := io.prci.interrupts.debug
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reg_dcsr.hwbpcount := UInt(p(NBreakpoints))
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reg_sptbr.asid := 0
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reg_tdrselect.reserved := 0
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reg_tdrselect.tdrmode := true // TODO support D-mode breakpoint theft
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if (reg_bp.isEmpty) reg_tdrselect.tdrindex := 0
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if (nBreakpoints <= 1) reg_tselect := 0
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if (nBreakpoints >= 1)
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reg_bp(nBreakpoints-1).control.chain := false
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for (bpc <- reg_bp map {_.control}) {
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bpc.tdrtype := bpc.tdrType
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bpc.bpamaskmax := bpc.bpaMaskMax
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bpc.ttype := bpc.tType
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bpc.maskmax := bpc.maskMax
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bpc.reserved := 0
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bpc.bpaction := 0
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bpc.zero := 0
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bpc.h := false
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if (!usingVM) bpc.s := false
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if (!usingUser) bpc.u := false
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if (!usingVM && !usingUser) bpc.m := true
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when (reset) {
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bpc.action := false
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bpc.dmode := false
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bpc.r := false
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bpc.w := false
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bpc.x := false
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}
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}
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for (bp <- reg_bp drop p(NBreakpoints))
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for (bp <- reg_bp drop nBreakpoints)
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bp := new BP().fromBits(0)
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def legalizePrivilege(priv: UInt): UInt =
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@ -280,10 +280,10 @@ object CSRs {
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val mscycle_delta = 0x704
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val mstime_delta = 0x705
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val msinstret_delta = 0x706
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val tdrselect = 0x7a0
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val tdrdata1 = 0x7a1
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val tdrdata2 = 0x7a2
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val tdrdata3 = 0x7a3
|
||||
val tselect = 0x7a0
|
||||
val tdata1 = 0x7a1
|
||||
val tdata2 = 0x7a2
|
||||
val tdata3 = 0x7a3
|
||||
val dcsr = 0x7b0
|
||||
val dpc = 0x7b1
|
||||
val dscratch = 0x7b2
|
||||
|
|
@ -346,10 +346,10 @@ object CSRs {
|
|||
res += mscycle_delta
|
||||
res += mstime_delta
|
||||
res += msinstret_delta
|
||||
res += tdrselect
|
||||
res += tdrdata1
|
||||
res += tdrdata2
|
||||
res += tdrdata3
|
||||
res += tselect
|
||||
res += tdata1
|
||||
res += tdata2
|
||||
res += tdata3
|
||||
res += dcsr
|
||||
res += dpc
|
||||
res += dscratch
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
|
|||
val usingRoCC = !p(BuildRoCC).isEmpty
|
||||
val fastLoadWord = p(FastLoadWord)
|
||||
val fastLoadByte = p(FastLoadByte)
|
||||
val nBreakpoints = p(NBreakpoints)
|
||||
|
||||
val retireWidth = p(RetireWidth)
|
||||
val fetchWidth = p(FetchWidth)
|
||||
|
|
@ -245,7 +246,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
val id_do_fence = id_rocc_busy && id_ctrl.fence ||
|
||||
id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en)
|
||||
|
||||
val bpu = Module(new BreakpointUnit)
|
||||
val bpu = Module(new BreakpointUnit(nBreakpoints))
|
||||
bpu.io.status := csr.io.status
|
||||
bpu.io.bp := csr.io.bp
|
||||
bpu.io.pc := ibuf.io.pc
|
||||
|
|
@ -254,6 +255,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
val id_xcpt_if = ibuf.io.inst(0).bits.pf0 || ibuf.io.inst(0).bits.pf1
|
||||
val (id_xcpt, id_cause) = checkExceptions(List(
|
||||
(csr.io.interrupt, csr.io.interrupt_cause),
|
||||
(bpu.io.debug_if, UInt(CSR.debugTriggerCause)),
|
||||
(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
|
||||
(id_xcpt_if, UInt(Causes.fault_fetch)),
|
||||
(id_illegal_insn, UInt(Causes.illegal_instruction))))
|
||||
|
|
@ -408,7 +410,9 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
}
|
||||
|
||||
val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
|
||||
val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)
|
||||
val (mem_new_xcpt, mem_new_cause) = checkExceptions(List(
|
||||
(mem_debug_breakpoint, UInt(CSR.debugTriggerCause)),
|
||||
(mem_breakpoint, UInt(Causes.breakpoint)),
|
||||
(mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
|
||||
(mem_ctrl.mem && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)),
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user