flatten Coreplex module hierarchy
This commit is contained in:
Yunsup Lee
parent
63679bb019
commit
a4c1942958
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@ -55,36 +55,96 @@ trait HasCoreplexParameters {
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lazy val exportMMIO = p(ExportMMIOPort)
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}
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/** Wrapper around everything that isn't a Tile.
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*
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* Usually this is clocked and/or place-and-routed separately from the Tiles.
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*/
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class Uncore(implicit val p: Parameters) extends Module
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abstract class Coreplex(implicit val p: Parameters) extends Module
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with HasCoreplexParameters {
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val io = new Bundle {
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class CoreplexIO(implicit val p: Parameters) extends Bundle {
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val tiles_slave = Vec(nTiles, new ClientUncachedTileLinkIO)
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val ext_uncached = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip
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val prci = Vec(nTiles, new PRCITileIO).asOutput
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val mmio = exportMMIO.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val ext_clients = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip
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val mmio = p(ExportMMIOPort).option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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val rtcTick = Bool(INPUT)
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val rtcTick = new Bool(INPUT)
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val extra = p(ExtraCoreplexPorts)(p)
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val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
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}
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val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0)
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Module(new DefaultOuterMemorySystem) // NoC, LLC and SerDes
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else Module(new DummyOuterMemorySystem)
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outmemsys.io.incoherent foreach (_ := false)
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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outmemsys.io.ext_uncached <> io.ext_uncached
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io.mem <> outmemsys.io.mem
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def hasSuccessFlag: Boolean = false
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val io = new CoreplexIO
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}
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buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"}))
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class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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// Build a set of Tiles
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val tileResets = Wire(Vec(nTiles, Bool()))
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val tileList = p(BuildTiles).zip(tileResets).map {
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case (tile, rst) => tile(rst, p)
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}
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val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
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printConfigString
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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case NCachedTileLinkPorts => nCachedPorts
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case NUncachedTileLinkPorts => nUncachedPorts
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}))
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def printConfigString(implicit p: Parameters) = {
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println("Generated Address Map")
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for (entry <- p(GlobalAddrMap).flatten) {
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val name = entry.name
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val start = entry.region.start
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val end = entry.region.start + entry.region.size - 1
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println(f"\t$name%s $start%x - $end%x")
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}
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println("Generated Configuration String")
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println(new String(p(ConfigString)))
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}
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def buildUncore(implicit p: Parameters) = {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = if (nBanks == 0) UInt(0) else {
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val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory, addr.extract(lsb + log2Ceil(nBanks) - 1, lsb), UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(1,1,2,2,0)
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.foreach { _.incoherent := Vec.fill(nCachedTilePorts)(Bool(false)) }
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val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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case TLId => "L1toL2"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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// Wire the tiles to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> tileList.map(_.io.cached).flatten
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l1tol2net.io.clients_uncached <> tileList.map(_.io.uncached).flatten ++ io.ext_clients
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostParams))
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val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
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TileLinkWidthAdapter(icPort, unwrap.io.out)
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}
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io.mem <> mem_ic.io.out
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buildMMIONetwork(ClientUncachedTileLinkEnqueuer(mmioManager.io.outer, 1))(
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p.alterPartial({case TLId => "L2toMMIO"}))
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}
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def makeBootROM()(implicit p: Parameters) = {
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val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
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@ -104,11 +164,12 @@ class Uncore(implicit val p: Parameters) extends Module
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rom.array() ++ p(ConfigString).toSeq
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}
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def buildMMIONetwork(implicit p: Parameters) = {
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def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val ioAddrMap = p(GlobalAddrMap).subMap("io")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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mmioNetwork.io.in.head <> outmemsys.io.mmio
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mmioNetwork.io.in.head <> mmio
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val plic = Module(new PLIC(p(PLICKey)))
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plic.io.tl <> mmioNetwork.port("int:plic")
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@ -124,168 +185,32 @@ class Uncore(implicit val p: Parameters) extends Module
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val prci = Module(new PRCI)
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prci.io.tl <> mmioNetwork.port("int:prci")
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io.prci := prci.io.tiles
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prci.io.rtcTick := io.rtcTick
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(prci.io.tiles, tileResets, tileList).zipped.foreach {
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case (prci, rst, tile) =>
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rst := reset
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tile.io.prci <> prci
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}
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for (i <- 0 until nTiles) {
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prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
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if (p(UseVM))
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prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
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prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
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io.prci(i).reset := reset
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}
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val tileSlavePorts = (0 until nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)
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for ((t, m) <- io.tiles_slave zip (tileSlavePorts map (mmioNetwork port _)))
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for ((t, m) <- (tileList.map(_.io.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _)))
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t <> ClientUncachedTileLinkEnqueuer(m, 1)
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val bootROM = Module(new ROMSlave(makeBootROM()))
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bootROM.io <> mmioNetwork.port("int:bootrom")
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io.mmio.map { ext => ext <> mmioNetwork.port("ext") }
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io.mmio.foreach { _ <> mmioNetwork.port("ext") }
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}
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}
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abstract class OuterMemorySystem(implicit val p: Parameters)
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extends Module with HasCoreplexParameters {
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val io = new Bundle {
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val ext_uncached = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip
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val incoherent = Vec(nCachedTilePorts, Bool()).asInput
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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}
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/** Use in place of OuterMemorySystem if there are no clients to connect. */
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class DummyOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem()(p) {
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require(nCachedTilePorts + nUncachedTilePorts + nExtClients == 0)
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io.mem.foreach { tl =>
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tl.acquire.valid := Bool(false)
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tl.grant.ready := Bool(false)
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}
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io.mmio.acquire.valid := Bool(false)
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io.mmio.grant.ready := Bool(false)
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}
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/** The whole outer memory hierarchy, including a NoC, some kind of coherence
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* manager agent, and a converter from TileLink to MemIO.
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*/
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class DefaultOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem()(p) {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = if (nBanks == 0) UInt(0) else {
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val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory, addr.extract(lsb + log2Ceil(nBanks) - 1, lsb), UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(1,1,2,2,0)
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.foreach { _.incoherent := io.incoherent }
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val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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case TLId => "L1toL2"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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io.mmio.acquire <> Queue(mmioManager.io.outer.acquire, 1)
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mmioManager.io.outer.grant <> Queue(io.mmio.grant, 1)
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// Wire the tiles to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> io.tiles_cached
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l1tol2net.io.clients_uncached <> io.tiles_uncached ++ io.ext_uncached
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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// TODO: the code to print this stuff should live somewhere else
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println("Generated Address Map")
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for (entry <- p(GlobalAddrMap).flatten) {
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val name = entry.name
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val start = entry.region.start
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val end = entry.region.start + entry.region.size - 1
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println(f"\t$name%s $start%x - $end%x")
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}
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println("Generated Configuration String")
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println(new String(p(ConfigString)))
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostParams))
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
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TileLinkWidthAdapter(icPort, unwrap.io.out)
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}
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io.mem <> mem_ic.io.out
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}
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abstract class Coreplex(implicit val p: Parameters) extends Module
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with HasCoreplexParameters {
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class CoreplexIO(implicit val p: Parameters) extends Bundle {
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val ext_clients = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip
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val mmio = p(ExportMMIOPort).option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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val rtcTick = new Bool(INPUT)
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val extra = p(ExtraCoreplexPorts)(p)
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val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
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}
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def hasSuccessFlag: Boolean = false
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val io = new CoreplexIO
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}
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class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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// Build an Uncore and a set of Tiles
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val tileResets = Wire(Vec(nTiles, Bool()))
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val tileList = p(BuildTiles).zip(tileResets).map {
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case (tile, rst) => tile(rst, p)
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}
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val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
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val innerTLParams = p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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case NCachedTileLinkPorts => nCachedPorts
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case NUncachedTileLinkPorts => nUncachedPorts
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})
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val uncore = Module(new Uncore()(innerTLParams))
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(uncore.io.prci, tileResets, tileList).zipped.foreach {
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case (prci, rst, tile) =>
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rst := prci.reset
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tile.io.prci <> prci
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}
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uncore.io.rtcTick := io.rtcTick
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
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(tileList.map(_.io.slave).flatten zip uncore.io.tiles_slave) foreach { case (x, y) => x <> y }
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uncore.io.interrupts <> io.interrupts
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uncore.io.debug <> io.debug
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uncore.io.ext_uncached <> io.ext_clients
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if (exportMMIO) { io.mmio.get <> uncore.io.mmio.get }
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io.mem <> uncore.io.mem
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}
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class GroundTestCoreplex(topParams: Parameters) extends DefaultCoreplex(topParams) {
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override def hasSuccessFlag = true
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io.success.get := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
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