riscv/rocket-chip
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Set default TileLink width to XLen

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This commit is contained in:
Andrew Waterman 2016-09-02 14:56:00 -07:00
parent e23e4d6de5
commit fb50f7c9dd
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/Configs.scala
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@ -27,7 +27,7 @@ class BaseCoreplexConfig extends Config (
topDefinitions = { (pname,site,here) =>
type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
lazy val innerDataBits = 64
lazy val innerDataBits = site(XLen)
lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
pname match {
//Memory Parameters