riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

make sure DummyPTW sets all the necessary status and ptbr signals

Browse Source
This commit is contained in:
Howard Mao 2016-08-30 14:43:00 -07:00
parent 403cc1c5c4
commit 50d6738caf
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/groundtest/Tile.scala
View File

@ -69,6 +69,11 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
requestor.resp.bits := s2_resp
requestor.status.vm := UInt("b01000")
requestor.status.prv := UInt(PRV.S)
requestor.status.debug := Bool(false)
requestor.status.mprv := Bool(true)
requestor.status.mpp := UInt(0)
requestor.ptbr.asid := UInt(0)
requestor.ptbr.ppn := UInt(0)
requestor.invalidate := Bool(false)
}
}