riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra ed9fcea7f8 hasti: correct fix to locking 2016-06-08 16:28:30 -07:00
Wesley W. Terpstra ad4e4f19be Revert "Don't rely on Mux1H output when no inputs are hot" 
This reverts commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970.
 2016-06-08 16:28:30 -07:00
Wesley W. Terpstra 3393d4362b hasti: fix test SRAM depth 2016-06-08 16:28:30 -07:00
Howard Mao 0969be8804 Revert "make sure SlowIO clock divider is initialized on reset" 
This reverts commit 546aaad8cfb03e45e068733c2b694232bcf9dcdb.
 2016-06-08 13:45:30 -07:00
Howard Mao 636a46c052 make sure SlowIO clock divider is initialized on reset 2016-06-08 10:02:21 -07:00
Andrew Waterman 28161cab45 Merge AddrHashMap and AddrMap 2016-06-03 13:46:53 -07:00
Wesley W. Terpstra 695be2f0ae hasti: work-around unsupported 0-width signals 2016-06-01 16:38:49 -07:00
Howard Mao 8983b0e865 hopefully the last fix for AXI -> AHB converter 2016-06-01 15:01:52 -07:00
Howard Mao 53a0e6cb9c another fix for AXI -> AHB converter 2016-06-01 11:35:36 -07:00
Howard Mao d0988902f2 fix NASTI -> HASTI bridge 2016-05-31 19:47:50 -07:00
Andrew Waterman 56897f707a Don't rely on Mux1H output when no inputs are hot 2016-05-27 13:38:01 -07:00
Andrew Waterman 056d7ec93a Drive hmastlock low in Nasti-Hasti converter 2016-05-27 12:23:18 -07:00
Andrew Waterman e036d3a04a Chisel3: gender issue 2016-05-26 15:59:08 -07:00
Andrew Waterman a2b9d337b6 No need for full-throughput queues in NastiErrorSlave 2016-05-26 01:03:40 -07:00
Andrew Waterman 2ece3e6102 Use Mem for ReorderQueue data 
This might improve FPGA QoR.
 2016-05-26 01:02:56 -07:00
Wesley W. Terpstra 1c8745dfd2 ahb: backport to chisel2 
Merges #16
 2016-05-25 12:11:26 -07:00
Donggyu a9599302bd fix cloneType in nasti.scala (#14) 2016-05-24 17:10:17 -07:00
Andrew Waterman 5bc78aba99 Merge pull request #15 from terpstra/ahb 
Ahb
 2016-05-24 17:06:03 -07:00
Wesley W. Terpstra b921bae107 ahb: eliminate trait abused for constants 2016-05-24 14:20:45 -07:00
Wesley W. Terpstra 200c69c106 ahb: support hmastlock acquistion of crossbar 2016-05-24 14:20:45 -07:00
Wesley W. Terpstra e1e8eda419 ahb: add a test SRAM 2016-05-24 14:20:42 -07:00
Wesley W. Terpstra 1db40687c6 ahb: eliminate now-unnecesary non-standard hreadyin 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra 15cad8414d ahb: put signals in the order they appear in signal traces in the spec 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra f30f8d9f79 ahb: reduce obsolete degenerate cases of a crossbar 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra 0368b6db6b ahb: replace defective crossbar with a functional one 
The previous crossbar had the following bugs:
  1. a bursting master could be preempted
     the AHB-lite spec requires a slave receive the entire burst

  2. a waited master could be replaced
     the AHB-lite spec requires haddr/etc to remain unchanged

  3. hmastlock did no ensure exclusive access
     atomic operations could be pre-empted
 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra 2b37f37335 ahb: helper methods 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra ef2aae26a8 ahb: rename hreadyout to standard hready, mark hreadyin for death 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra 2f8a77f27a ahb: include all AHB-lite constants 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra 7896c4157e ahb: parameterize poci 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra 93447eb274 ahb: make hasti parameters location sensitive 2016-05-24 14:14:17 -07:00
Howard Mao 44740cb6b2 parameterize Hasti address and data bits 2016-05-06 11:30:50 -07:00
Howard Mao 64991d3947 add AXI to AHB converter 2016-05-06 11:30:50 -07:00
Howard Mao be21f6962b make GlobalAddrHashMap a config variable 2016-05-02 18:22:43 -07:00
Andrew Waterman e4ace55d77 Address Map refactoring 2016-04-28 16:12:35 -07:00
Andrew Waterman c8b1f0801b Remove start address option from AddrMapEntries 
It appears to never be used, and clutters things.  The new invariant is
that AddrMaps are relative and AddrHashMaps are absolute.
 2016-04-27 14:52:05 -07:00
Andrew Waterman d3dee2c6c6 support countSlaves on empty address maps 2016-04-27 14:51:52 -07:00
Howard Mao 6260ad56e8 stop using MMIOBase and encode cacheability in address map 2016-04-21 15:33:53 -07:00
Howard Mao 1967186a96 add id field to NastiWriteDataChannel 2016-04-19 09:39:45 -07:00
Howard Mao 42c4d1e51f add NastiMemoryDemux 2016-04-19 09:39:15 -07:00
Howard Mao 0bf8d07aba make AtosSerializedIO clock divisible 2016-04-19 09:39:15 -07:00
Howard Mao 1dc8af894e fix serializer/deserializer and add Atos serdes/desser 2016-04-19 09:39:15 -07:00
Howard Mao d66d8f0cd4 fix SMI converter 2016-04-01 18:32:15 -07:00
Howard Mao 015992bc9e no longer need MIFMasterTagBits 2016-03-28 12:24:11 -07:00
Howard Mao 34852e406d fix bug in NastiRouter 2016-03-28 12:22:43 -07:00
Eric Love db09f310a1 Define MIFMasterTagBits as # bits a master can *use* in tag 2016-03-11 16:48:13 -08:00
Howard Mao 4f5b1da58b add a resp_len helper to AtosRequest 2016-02-23 16:24:32 -08:00
Howard Mao db3b2c264c Add constructors, converters, and serdes for AXI tunneled over SERDES (AtoS) 2016-02-23 16:24:32 -08:00
Howard Mao fbd66ac87b expose a count in MultiWidthFifo 2016-02-19 11:20:43 -08:00
Howard Mao 5241ee6442 add multi-width FIFO 2016-02-19 11:20:43 -08:00
Palmer Dabbelt 770f2742de Make NastiMemorySelector a subtype of NastiInterconnect 
When RocketChip has a single memory configuration I want to ensure no extra
hardware is being generated by only instantiating a NastiMemoryInterconnect
rather than a NastiMemorySelector, which I believe will insert a Mux with 0
when there is only one config (because there aren't any 0-width wires allowed).
 2016-02-17 10:41:01 -08:00