riscv/rocket-chip
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e85c54cc4b08cf78e86f752733ef3ef931e96371
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236 Commits

Author SHA1 Message Date
Andrew Waterman e85c54cc4b New privileged ISA implementation 2015-03-14 02:49:07 -07:00
Yunsup Lee ea018b3d84 stall rocket decode when not rocc ready 2015-03-11 22:33:03 -07:00
Christopher Celio 06dea3790a Removed sret from ptw; sret now comes thru io.cpu to dcache 2015-03-03 16:50:41 -08:00
Henry Cook 741e6b77ad Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
Andrew Waterman a98127c09e Merge branch 'ss-frontend' 2015-01-04 20:26:38 -08:00
Andrew Waterman b70f7683d3 Merge branch 'master' into ss-frontend 
Conflicts:
	src/main/scala/ctrl.scala
 2015-01-04 19:59:18 -08:00
Andrew Waterman 87ad1a5703 More control cleanup 2015-01-04 19:46:01 -08:00
Andrew Waterman 2aee85cb11 Flush pipeline from MEM stage 
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control.  But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
 2015-01-04 16:40:16 -08:00
Andrew Waterman 94b75c7cb1 Continue refactoring control 2015-01-04 15:32:05 -08:00
Andrew Waterman 6181de4cc9 Much refactor, so control 2015-01-03 13:34:38 -08:00
Christopher Celio f19b3ca43e Deleted extra spaces at EOL in ctrl.scala 2014-11-16 22:04:33 -08:00
Christopher Celio 6749f67b7f Fixed BHT update error. 
- separated out BTB/BHT update
   - BHT updates counters on every branch
   - BTB update only on mispredicted and taken branches
 2014-11-16 22:02:27 -08:00
Christopher Celio fea31d2167 Significant changes and fixes to BTB for superscalar fetch. 
- BTBUpdate only occurs on mispredicts now.
   - RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
      Decode).
   - Added optional 2nd CAM port to BTB for updates (for when updates to the
      BTB may occur out-of-order).
   - Fixed resp.mask bit logic.
 2014-11-11 03:34:05 -08:00
Andrew Waterman 7bb7299018 Don't pollute BTB with PC+4 target predictions 2014-10-14 17:28:37 -07:00
Yunsup Lee 8abf62fae3 add LICENSE 2014-09-12 18:06:41 -07:00
Henry Cook 2de268b3b1 Cache utility traits. Completely compiles, asm tests hang. 2014-08-19 11:38:20 -07:00
Henry Cook 0dac9a7467 Full conversion to params. Compiles but does not elaborate. 2014-08-19 11:38:02 -07:00
Adam Izraelevitz 4e6d69892d Added initial brainstorm for parameter hierarchical flattening, does not compile ;) 2014-08-19 11:37:50 -07:00
Adam Izraelevitz 812353bace Ported FPU parameters to new Chisel Parameters 2014-08-19 11:37:27 -07:00
Andrew Waterman 3828c628c3 Remove vestigial control signals 2014-06-14 13:58:07 -07:00
Andrew Waterman ac88ded35a Use ROMs to reduce node count and improve QoR a bit 2014-06-14 13:58:07 -07:00
Henry Cook 1fa505f9ff remove superfluous AVec object 2014-04-16 17:19:32 -07:00
Andrew Waterman 3520620fbd Remove D$ -> BTB path 2014-04-15 23:05:02 -07:00
Andrew Waterman de492b3cf7 Fix critical path through integer scoreboard 2014-04-15 21:28:13 -07:00
Andrew Waterman f235fa0db6 Move branch resolution to M stage 2014-04-07 15:58:49 -07:00
Andrew Waterman db59fc65ab Add return address stack 2014-04-01 15:01:27 -07:00
Andrew Waterman 1b030777ce Remove vestigial control signal 2014-03-24 04:36:12 -07:00
Andrew Waterman 943d7ac80a Use LinkedHashSet/Map for simpler determinism 2014-03-15 17:31:48 -07:00
Donggyu Kim 53d62cb69d remove nondeterminism 2014-03-15 16:45:58 -07:00
Andrew Waterman 00bc1a2293 Add fclass.{s|d} instructions 2014-03-10 16:59:24 -07:00
Andrew Waterman c7110c8389 Make FPU pipeline depths configurable 2014-02-28 13:39:59 -08:00
Andrew Waterman a09ff9fdc7 Revert to old AUIPC definition 2014-02-10 19:04:42 -08:00
Andrew Waterman 1456170c6d Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence 2014-02-06 12:01:49 -08:00
Yunsup Lee ff7cae29f7 hookup rocc interrupt and s bit 2014-02-06 00:09:42 -08:00
Stephen Twigg 6a02d15c21 Merge branch 'master' into hwacha-port 2014-02-04 17:05:03 -08:00
Andrew Waterman febd26f505 Correct CSR privilege logic 2014-01-31 01:03:17 -08:00
Stephen Twigg 3c3c469725 Add exception signal to rocc interface 2014-01-28 22:13:16 -08:00
Andrew Waterman 267394d3cc Fix CSR interlocks 2014-01-24 16:37:40 -08:00
Andrew Waterman 1f986d1c96 Branches don't care about the ALU input/function 2014-01-24 16:37:40 -08:00
Andrew Waterman a1b7774f5d Simplify handling of CAUSE register 2014-01-24 16:37:39 -08:00
Andrew Waterman 6ba2c1abe5 Use auto-generated CAUSE constants 2014-01-21 15:01:54 -08:00
Andrew Waterman 57f4d89c90 Generate D$ replay_next signals correctly 2014-01-16 00:16:09 -08:00
Andrew Waterman 31060ea8ae Fix fubar long-latency writeback control logic 
Load miss writebacks happening at the same time as multiplication
wasn't working.  Hopefully this does it.
 2014-01-14 04:02:43 -08:00
Andrew Waterman e8486817e6 Clean up formatting (i.e. remove tabs, semicolons) 2014-01-13 21:43:56 -08:00
Andrew Waterman 07a91bb99a Miscellaneous cleanup 2013-12-09 19:53:14 -08:00
Andrew Waterman da3135ac9b Begin integer unit clean-up 
...to make it easier to generate the superscalar version of the core.
 2013-12-09 15:06:13 -08:00
Andrew Waterman 16d5250924 Correct FP trap behavior on FCSR 2013-12-05 04:18:04 -08:00
Andrew Waterman 924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Andrew Waterman 65b8340cea Mitigate D$ hit -> branch -> NPC critical path 2013-11-24 14:21:03 -08:00
Stephen Twigg 3532ae0b79 From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator). 2013-09-24 10:54:09 -07:00