Andrew Waterman
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e496cd7584
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use Mem to implement queues to speed things up
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2012-07-13 21:48:05 -07:00 |
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Huy Vo
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a79747a062
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Huy Vo
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18bc14058b
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Huy Vo
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Andrew Waterman
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bac82762d3
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use only one (wide) tag ram for set assoc. caches
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2012-07-12 14:50:12 -07:00 |
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Andrew Waterman
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62a3ea4113
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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0aa33bf909
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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429fcbed8e
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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1ebfeeca8a
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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Andrew Waterman
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66cf690261
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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Andrew Waterman
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f645fb4dd7
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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Andrew Waterman
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5035374f36
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update to new chisel
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2012-07-08 17:59:41 -07:00 |
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Andrew Waterman
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39d198ecdc
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fix htif handling of large memory reads
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2012-06-26 19:12:11 -07:00 |
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Andrew Waterman
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4e5f874266
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update to new chisel/hwacha
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2012-06-08 00:13:14 -07:00 |
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Huy Vo
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166b857055
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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0c6bade592
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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a99cebb483
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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9b3161920f
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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f2942f79f9
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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c975c21e44
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views removed
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2012-06-06 12:51:26 -07:00 |
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Andrew Waterman
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943b6d0616
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remove debug println
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2012-06-06 02:48:48 -07:00 |
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Andrew Waterman
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7f6319047e
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update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
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Huy Vo
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6f2f1ba21c
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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0208e9f95e
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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181b20d69c
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working vec unit with pvfb
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2012-05-24 10:38:14 -07:00 |
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Andrew Waterman
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faee45bf4c
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fix setpcr/clearpcr not writing rd
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2012-05-21 07:25:35 -07:00 |
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Yunsup Lee
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c9602a0d2e
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fix vector control decode bug
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2012-05-15 10:26:37 -07:00 |
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Gage W Eads
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d0bc995c88
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Fixed IRQ_IPI -> IRQ_TIMER typo
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2012-05-14 22:25:12 -07:00 |
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Andrew Waterman
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a2f6d01c1b
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add programmable coreid register
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2012-05-09 03:09:22 -07:00 |
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Andrew Waterman
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e0e1cd5d32
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add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
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2012-05-08 22:58:00 -07:00 |
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Henry Cook
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87cbae2c8a
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Removed defunct ioDmem
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2012-05-07 17:31:39 -07:00 |
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Andrew Waterman
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b851f1b34c
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support maximum-MTU HTIF packets
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2012-05-03 21:11:43 -07:00 |
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Andrew Waterman
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f804c57bb0
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reduce HTIF clock divider for now
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2012-05-03 04:21:11 -07:00 |
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Andrew Waterman
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171c87002e
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reduce HTIF clock divider for now
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2012-05-03 04:21:11 -07:00 |
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Andrew Waterman
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e1f9dc2c1f
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generalize page table walker
also, don't instantiate vitlb when !HAVE_VEC
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2012-05-03 02:29:09 -07:00 |
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Andrew Waterman
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2d4e5d3813
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fix pseudo-LRU verilog generation bug
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2012-05-02 19:31:31 -07:00 |
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Henry Cook
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622a801bb1
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Refactored cpu/cache interface to use nested bundles
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2012-05-02 11:54:28 -07:00 |
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Andrew Waterman
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65ff397122
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improved instruction decoding
it now makes use of don't-cares by performing logic minimization
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2012-05-01 20:16:36 -07:00 |
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Andrew Waterman
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4cfa6cd9a8
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force Top.main's return type to Unit
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2012-05-01 19:55:16 -07:00 |
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Andrew Waterman
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5819beed64
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use parameterized FP units
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2012-05-01 01:25:43 -07:00 |
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Andrew Waterman
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eafdffe125
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simplify page table walker; speed up emulator
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2012-05-01 01:24:36 -07:00 |
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Andrew Waterman
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c13d3e6f88
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fix probe tag read-modify-write atomicity violation
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2012-04-26 02:29:31 -07:00 |
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Andrew Waterman
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66f86a2194
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use pseudo-LRU replacement for TLBs
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2012-04-26 02:29:30 -07:00 |
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Andrew Waterman
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a0378c5d2f
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remove faulting TLB entry after page fault
this vastly reduces the frequency with which the TLB must be flushed
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2012-04-26 02:29:30 -07:00 |
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Andrew Waterman
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6d8fc74378
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fix DTLB permissions bug
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2012-04-26 02:29:30 -07:00 |
|
Henry Cook
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99bc99f2ad
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Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
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2012-04-24 17:17:42 -07:00 |
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Henry Cook
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00155f4bc4
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Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
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2012-04-24 17:17:42 -07:00 |
|
Henry Cook
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1ed89f1cab
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Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
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2012-04-24 17:17:42 -07:00 |
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