INPUT/OUTPUT orderring swapped
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62a3ea4113
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@ -7,7 +7,7 @@ import Constants._
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class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) extends Component
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{
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val io = new Bundle {
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val addr = UFix(log2Up(n), INPUT)
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val addr = UFix(INPUT, log2Up(n))
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val en = Bool(INPUT)
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val rw = Bool(INPUT)
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val wdata = gen.asInput
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@ -99,17 +99,17 @@ class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Component
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{
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val io = new Bundle {
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val cpu = (new FIFOIO) { new MemReqCmd }.flip
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val repl_way = UFix(log2Up(ways), INPUT)
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val repl_way = UFix(INPUT, log2Up(ways))
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val repl_dirty = Bool(INPUT)
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val repl_tag = UFix(PADDR_BITS - OFFSET_BITS - log2Up(sets), INPUT)
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val repl_tag = UFix(INPUT, PADDR_BITS - OFFSET_BITS - log2Up(sets))
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val data = (new FIFOIO) { new LLCDataReq(ways) }
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val tag = (new FIFOIO) { new Bundle {
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val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
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val way = UFix(width = log2Up(ways))
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} }
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val mem = new ioMem
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val mem_resp_set = UFix(log2Up(sets), OUTPUT)
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val mem_resp_way = UFix(log2Up(ways), OUTPUT)
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val mem_resp_set = UFix(OUTPUT, log2Up(sets))
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val mem_resp_way = UFix(OUTPUT, log2Up(ways))
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}
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class MSHR extends Bundle {
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@ -247,8 +247,8 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
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val writeback_data = (new FIFOIO) { new MemData }
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val resp = (new PipeIO) { new MemResp }
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val mem_resp = (new PipeIO) { new MemResp }.flip
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val mem_resp_set = UFix(log2Up(sets), INPUT)
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val mem_resp_way = UFix(log2Up(ways), INPUT)
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val mem_resp_set = UFix(INPUT, log2Up(sets))
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val mem_resp_way = UFix(INPUT, log2Up(ways))
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}
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val data = new BigMem(sets*ways*REFILL_CYCLES, 2, leaf)(Bits(width = MEM_DATA_BITS))
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@ -56,8 +56,8 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
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val p_data = (new PipeIO) { new TrackerProbeData }.flip
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val can_alloc = Bool(INPUT)
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val xact_finish = Bool(INPUT)
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val p_rep_cnt_dec = Bits(ntiles, INPUT)
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val p_req_cnt_inc = Bits(ntiles, INPUT)
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val p_rep_cnt_dec = Bits(INPUT, ntiles)
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val p_req_cnt_inc = Bits(INPUT, ntiles)
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val p_rep_data = (new PipeIO) { new ProbeReplyData }.flip
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val x_init_data = (new PipeIO) { new TransactionInitData }.flip
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val sent_x_rep_ack = Bool(INPUT)
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@ -69,19 +69,19 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
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val mem_req_lock = Bool(OUTPUT)
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val probe_req = (new FIFOIO) { new ProbeRequest }
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS - OFFSET_BITS, OUTPUT)
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val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val p_rep_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS+1, OUTPUT)
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val x_type = Bits(X_INIT_TYPE_MAX_BITS, OUTPUT)
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val push_p_req = Bits(ntiles, OUTPUT)
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val pop_p_rep = Bits(ntiles, OUTPUT)
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val pop_p_rep_data = Bits(ntiles, OUTPUT)
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val pop_p_rep_dep = Bits(ntiles, OUTPUT)
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val pop_x_init = Bits(ntiles, OUTPUT)
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val pop_x_init_data = Bits(ntiles, OUTPUT)
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val pop_x_init_dep = Bits(ntiles, OUTPUT)
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val addr = Bits(OUTPUT, PADDR_BITS - OFFSET_BITS)
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val init_tile_id = Bits(OUTPUT, TILE_ID_BITS)
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val p_rep_tile_id = Bits(OUTPUT, TILE_ID_BITS)
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val tile_xact_id = Bits(OUTPUT, TILE_XACT_ID_BITS)
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val sharer_count = Bits(OUTPUT, TILE_ID_BITS+1)
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val x_type = Bits(OUTPUT, X_INIT_TYPE_MAX_BITS)
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val push_p_req = Bits(OUTPUT, ntiles)
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val pop_p_rep = Bits(OUTPUT, ntiles)
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val pop_p_rep_data = Bits(OUTPUT, ntiles)
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val pop_p_rep_dep = Bits(OUTPUT, ntiles)
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val pop_x_init = Bits(OUTPUT, ntiles)
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val pop_x_init_data = Bits(OUTPUT, ntiles)
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val pop_x_init_dep = Bits(OUTPUT, ntiles)
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val send_x_rep_ack = Bool(OUTPUT)
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}
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