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ioDecoupled -> FIFOIO, ioPipe -> PipeIO

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This commit is contained in:
Huy Vo 2012-06-06 18:22:56 -07:00
parent 9b3161920f
commit 166b857055
3 changed files with 28 additions and 28 deletions
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4
uncore/memserdes.scala
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@ -7,8 +7,8 @@ import scala.math._
class ioMemSerialized extends Bundle
{
val req = (new ioDecoupled) { Bits(width = MEM_BACKUP_WIDTH) }
val resp = (new ioPipe) { Bits(width = MEM_BACKUP_WIDTH) }.flip
val req = (new FIFOIO) { Bits(width = MEM_BACKUP_WIDTH) }
val resp = (new PipeIO) { Bits(width = MEM_BACKUP_WIDTH) }.flip
}
class MemSerdes extends Component

8
uncore/slowio.scala
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@ -6,11 +6,11 @@ import Constants._
class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T) extends Component
{
val io = new Bundle {
val out_fast = new ioDecoupled()(data).flip
val out_slow = new ioDecoupled()(data)
val out_fast = new FIFOIO()(data).flip
val out_slow = new FIFOIO()(data)
val in_fast = new ioDecoupled()(data)
val in_slow = new ioDecoupled()(data).flip
val in_fast = new FIFOIO()(data)
val in_slow = new FIFOIO()(data).flip
val clk_slow = Bool(OUTPUT)
}

44
uncore/uncore.scala
View File

@ -21,9 +21,9 @@ class MemResp () extends MemData
class ioMem() extends Bundle
{
val req_cmd = (new ioDecoupled) { new MemReqCmd() }
val req_data = (new ioDecoupled) { new MemData() }
val resp = (new ioPipe) { new MemResp() }.flip
val req_cmd = (new FIFOIO) { new MemReqCmd() }
val req_data = (new FIFOIO) { new MemData() }
val resp = (new PipeIO) { new MemResp() }.flip
}
class TrackerProbeData extends Bundle {
@ -40,34 +40,34 @@ class TrackerDependency extends Bundle {
}
class ioTileLink extends Bundle {
val xact_init = (new ioDecoupled) { new TransactionInit }
val xact_init_data = (new ioDecoupled) { new TransactionInitData }
val xact_abort = (new ioDecoupled) { new TransactionAbort }.flip
val probe_req = (new ioDecoupled) { new ProbeRequest }.flip
val probe_rep = (new ioDecoupled) { new ProbeReply }
val probe_rep_data = (new ioDecoupled) { new ProbeReplyData }
val xact_rep = (new ioPipe) { new TransactionReply }.flip
val xact_finish = (new ioDecoupled) { new TransactionFinish }
val xact_init = (new FIFOIO) { new TransactionInit }
val xact_init_data = (new FIFOIO) { new TransactionInitData }
val xact_abort = (new FIFOIO) { new TransactionAbort }.flip
val probe_req = (new FIFOIO) { new ProbeRequest }.flip
val probe_rep = (new FIFOIO) { new ProbeReply }
val probe_rep_data = (new FIFOIO) { new ProbeReplyData }
val xact_rep = (new PipeIO) { new TransactionReply }.flip
val xact_finish = (new FIFOIO) { new TransactionFinish }
}
class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
val io = new Bundle {
val alloc_req = (new ioDecoupled) { new TrackerAllocReq }.flip
val p_data = (new ioPipe) { new TrackerProbeData }.flip
val alloc_req = (new FIFOIO) { new TrackerAllocReq }.flip
val p_data = (new PipeIO) { new TrackerProbeData }.flip
val can_alloc = Bool(INPUT)
val xact_finish = Bool(INPUT)
val p_rep_cnt_dec = Bits(ntiles, INPUT)
val p_req_cnt_inc = Bits(ntiles, INPUT)
val p_rep_data = (new ioPipe) { new ProbeReplyData }.flip
val x_init_data = (new ioPipe) { new TransactionInitData }.flip
val p_rep_data = (new PipeIO) { new ProbeReplyData }.flip
val x_init_data = (new PipeIO) { new TransactionInitData }.flip
val sent_x_rep_ack = Bool(INPUT)
val p_rep_data_dep = (new ioPipe) { new TrackerDependency }.flip
val x_init_data_dep = (new ioPipe) { new TrackerDependency }.flip
val p_rep_data_dep = (new PipeIO) { new TrackerDependency }.flip
val x_init_data_dep = (new PipeIO) { new TrackerDependency }.flip
val mem_req_cmd = (new ioDecoupled) { new MemReqCmd }
val mem_req_data = (new ioDecoupled) { new MemData }
val mem_req_cmd = (new FIFOIO) { new MemReqCmd }
val mem_req_data = (new FIFOIO) { new MemData }
val mem_req_lock = Bool(OUTPUT)
val probe_req = (new ioDecoupled) { new ProbeRequest }
val probe_req = (new FIFOIO) { new ProbeRequest }
val busy = Bool(OUTPUT)
val addr = Bits(PADDR_BITS - OFFSET_BITS, OUTPUT)
val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
@ -85,7 +85,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
val send_x_rep_ack = Bool(OUTPUT)
}
def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioPipe[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, tile_id: UFix) {
def doMemReqWrite(req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: PipeIO[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, tile_id: UFix) {
req_cmd.valid := !cmd_sent && data.valid && at_front_of_dep_queue
req_cmd.bits.rw := Bool(true)
req_data.valid := data.valid && at_front_of_dep_queue
@ -106,7 +106,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
}
}
def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) {
req_cmd.valid := Bool(true)
req_cmd.bits.rw := Bool(false)
when(req_cmd.ready) {