riscv/rocket-chip
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INPUT/OUTPUT orderring swapped

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This commit is contained in:
Huy Vo 2012-07-12 18:12:49 -07:00
parent 0aa33bf909
commit 18bc14058b
2 changed files with 22 additions and 22 deletions
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14
uncore/llc.scala
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@ -7,7 +7,7 @@ import Constants._
class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) extends Component
{
val io = new Bundle {
val addr = UFix(log2Up(n), INPUT)
val addr = UFix(INPUT, log2Up(n))
val en = Bool(INPUT)
val rw = Bool(INPUT)
val wdata = gen.asInput
@ -99,17 +99,17 @@ class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Component
{
val io = new Bundle {
val cpu = (new FIFOIO) { new MemReqCmd }.flip
val repl_way = UFix(log2Up(ways), INPUT)
val repl_way = UFix(INPUT, log2Up(ways))
val repl_dirty = Bool(INPUT)
val repl_tag = UFix(PADDR_BITS - OFFSET_BITS - log2Up(sets), INPUT)
val repl_tag = UFix(INPUT, PADDR_BITS - OFFSET_BITS - log2Up(sets))
val data = (new FIFOIO) { new LLCDataReq(ways) }
val tag = (new FIFOIO) { new Bundle {
val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
val way = UFix(width = log2Up(ways))
} }
val mem = new ioMem
val mem_resp_set = UFix(log2Up(sets), OUTPUT)
val mem_resp_way = UFix(log2Up(ways), OUTPUT)
val mem_resp_set = UFix(OUTPUT, log2Up(sets))
val mem_resp_way = UFix(OUTPUT, log2Up(ways))
}
class MSHR extends Bundle {
@ -247,8 +247,8 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
val writeback_data = (new FIFOIO) { new MemData }
val resp = (new PipeIO) { new MemResp }
val mem_resp = (new PipeIO) { new MemResp }.flip
val mem_resp_set = UFix(log2Up(sets), INPUT)
val mem_resp_way = UFix(log2Up(ways), INPUT)
val mem_resp_set = UFix(INPUT, log2Up(sets))
val mem_resp_way = UFix(INPUT, log2Up(ways))
}
val data = new BigMem(sets*ways*REFILL_CYCLES, 2, leaf)(Bits(width = MEM_DATA_BITS))

30
uncore/uncore.scala
View File

@ -56,8 +56,8 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
val p_data = (new PipeIO) { new TrackerProbeData }.flip
val can_alloc = Bool(INPUT)
val xact_finish = Bool(INPUT)
val p_rep_cnt_dec = Bits(ntiles, INPUT)
val p_req_cnt_inc = Bits(ntiles, INPUT)
val p_rep_cnt_dec = Bits(INPUT, ntiles)
val p_req_cnt_inc = Bits(INPUT, ntiles)
val p_rep_data = (new PipeIO) { new ProbeReplyData }.flip
val x_init_data = (new PipeIO) { new TransactionInitData }.flip
val sent_x_rep_ack = Bool(INPUT)
@ -69,19 +69,19 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
val mem_req_lock = Bool(OUTPUT)
val probe_req = (new FIFOIO) { new ProbeRequest }
val busy = Bool(OUTPUT)
val addr = Bits(PADDR_BITS - OFFSET_BITS, OUTPUT)
val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
val p_rep_tile_id = Bits(TILE_ID_BITS, OUTPUT)
val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
val sharer_count = Bits(TILE_ID_BITS+1, OUTPUT)
val x_type = Bits(X_INIT_TYPE_MAX_BITS, OUTPUT)
val push_p_req = Bits(ntiles, OUTPUT)
val pop_p_rep = Bits(ntiles, OUTPUT)
val pop_p_rep_data = Bits(ntiles, OUTPUT)
val pop_p_rep_dep = Bits(ntiles, OUTPUT)
val pop_x_init = Bits(ntiles, OUTPUT)
val pop_x_init_data = Bits(ntiles, OUTPUT)
val pop_x_init_dep = Bits(ntiles, OUTPUT)
val addr = Bits(OUTPUT, PADDR_BITS - OFFSET_BITS)
val init_tile_id = Bits(OUTPUT, TILE_ID_BITS)
val p_rep_tile_id = Bits(OUTPUT, TILE_ID_BITS)
val tile_xact_id = Bits(OUTPUT, TILE_XACT_ID_BITS)
val sharer_count = Bits(OUTPUT, TILE_ID_BITS+1)
val x_type = Bits(OUTPUT, X_INIT_TYPE_MAX_BITS)
val push_p_req = Bits(OUTPUT, ntiles)
val pop_p_rep = Bits(OUTPUT, ntiles)
val pop_p_rep_data = Bits(OUTPUT, ntiles)
val pop_p_rep_dep = Bits(OUTPUT, ntiles)
val pop_x_init = Bits(OUTPUT, ntiles)
val pop_x_init_data = Bits(OUTPUT, ntiles)
val pop_x_init_dep = Bits(OUTPUT, ntiles)
val send_x_rep_ack = Bool(OUTPUT)
}