removing wires
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@ -96,7 +96,7 @@ abstract class IncoherentPolicy extends CoherencePolicy {
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// UNIMPLEMENTED
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val reply = new ProbeReply()
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reply.p_type := UFix(0)
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reply.global_xact_id := UFix(0)
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reply
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@ -209,7 +209,7 @@ class MICoherence extends CoherencePolicyWithUncached {
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val reply = new ProbeReply()
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> probeRepInvalidateData,
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probeReqCopy -> probeRepCopyData
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@ -336,7 +336,7 @@ class MEICoherence extends CoherencePolicyWithUncached {
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val reply = new ProbeReply()
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> probeRepInvalidateData,
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probeReqDowngrade -> probeRepDowngradeData,
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@ -475,7 +475,7 @@ class MSICoherence extends CoherencePolicyWithUncached {
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val reply = new ProbeReply()
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> probeRepInvalidateData,
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probeReqDowngrade -> probeRepDowngradeData,
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@ -614,7 +614,7 @@ class MESICoherence extends CoherencePolicyWithUncached {
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val reply = new ProbeReply()
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> probeRepInvalidateData,
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probeReqDowngrade -> probeRepDowngradeData,
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@ -281,20 +281,20 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
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{
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(ntiles, _, co))
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val busy_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS-OFFSET_BITS)} }
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val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val x_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_MAX_BITS)} }
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val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val busy_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val addr_arr = Vec(NGLOBAL_XACTS){ Bits(width=PADDR_BITS-OFFSET_BITS) }
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val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=TILE_ID_BITS) }
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val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=TILE_XACT_ID_BITS) }
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val x_type_arr = Vec(NGLOBAL_XACTS){ Bits(width=X_INIT_TYPE_MAX_BITS) }
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val sh_count_arr = Vec(NGLOBAL_XACTS){ Bits(width=TILE_ID_BITS) }
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val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Wire(){Bool()} } }
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val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Wire(){Bool()} } }
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val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
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val p_data_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bits(width = TILE_ID_BITS)} }
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val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Bool()} }
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val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Bool()} }
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val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val p_data_tile_id_arr = Vec(NGLOBAL_XACTS){ Bits(width = TILE_ID_BITS) }
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val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() }
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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@ -410,13 +410,13 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
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// Nack conflicting transaction init attempts
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val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() }
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val abort_state_arr = Vec(ntiles) { Reg(resetVal = s_idle) }
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val want_to_abort_arr = Vec(ntiles) { Wire() { Bool()} }
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val want_to_abort_arr = Vec(ntiles) { Bool() }
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for( j <- 0 until ntiles ) {
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val x_init = io.tiles(j).xact_init
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val x_init_data = io.tiles(j).xact_init_data
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val x_abort = io.tiles(j).xact_abort
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val abort_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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val conflicts = Vec(NGLOBAL_XACTS) { Wire() { Bool() } }
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val conflicts = Vec(NGLOBAL_XACTS) { Bool() }
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.address)
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