ef7a6115b7
vsim: don't need VPI without JTAGVPI
2018-03-07 10:58:09 -08:00
64b707cbb6
Bump Chisel and FIRRTL for annotations refactor ( #1261 )
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Also brings in an autoclonetype enhancement and some bug fixes
2018-03-07 10:22:38 -08:00
4bcc42550e
Remove JTAG vpi from VCS build
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h/t @mwachs5
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com >
2018-02-26 15:12:18 -05:00
d0e350976a
Add jtag_vpi.c to sources for vsim
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com >
2018-02-23 17:31:24 -05:00
e26363a176
Don't pass deprecated -ffaaf option to firrtl ( #1221 )
2018-02-01 14:46:38 -08:00
e82328336e
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
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This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
3df401eef7
Bump chisel3 and firrtl and bump sbt to version 1.0.4
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sbt bump must be accompanied by bump to chisel3 and firrtl using sbt
1.0.4
2017-12-18 12:09:21 -08:00
6f3a4cd733
build: pass annotations to firrtl
2017-10-10 23:42:55 -07:00
ea4b1bc349
Use vlsi_mem_gen for verilator flow
2017-08-07 20:36:22 -07:00
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
7f1d3c445f
Plusargs -- tilelink timeout detection from the command line ( #752 )
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* util: PlusArg gives Chisel access to the command-line
* tilelink2: add a progress watchdog to Monitors
2017-05-18 22:49:59 -07:00
2119df5a60
vsrc: add ClockDivider3 used to simulate unaligned clocks
2017-05-14 15:05:55 -07:00
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
9f85b2e996
Do allow make to remove .vpd files on Ctrl-C
2017-03-30 00:36:23 -07:00
cbc8d2400a
debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version
2017-03-27 21:24:44 -07:00
4af437fdab
RANDOMIZE_MEM_INIT vlsi_mem_gen ( #572 )
2017-03-07 01:56:15 -08:00
91d1880dbf
ClockDivider2: fix launch alignment of clocks (vcs)
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Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.
See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
2017-02-17 14:26:23 +01:00
93b2fa197e
Artefact output ( #545 )
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* build: stop using empty .prm file
* generator: general-purpose mechanism for creating elaboration artefacts
2017-02-02 19:24:55 -08:00
8157cf1ede
Perform integer division when parsing rocketchip.DefaultConfig.conf ( #493 )
2017-01-13 16:40:02 -08:00
f19d504c88
Use % in makefrag-verilog to prevent double firrtl execution ( #452 )
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* Use % in makefrag-verilog to prevent double firrtl execution
2016-11-25 01:50:01 -08:00
f3c726033a
Make all Chisel invocations depend on FIRRTL_JAR
2016-10-28 11:56:05 -07:00
288d7169ae
Bump firrtl and update vsim Makefrag-verilog ( #409 )
2016-10-23 23:07:47 -07:00
7f429e8799
Simplify AsyncResetReg
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No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
2016-10-08 21:29:40 -07:00
77a0f76289
Cleanup jtag dtm ( #342 )
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* debug: Clean up Debug TransportModule synchronizer
With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.
I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
2016-09-26 11:10:27 -07:00
1e54820f8c
Merge remote-tracking branch 'origin/master' into unittest-config
2016-09-22 16:03:51 -07:00
411ee378de
Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.
2016-09-22 15:59:29 -07:00
cd96a66ba6
replace verilog clock divider with one written in Chisel
2016-09-22 11:32:29 -07:00
8e63f4a1a5
Remove ClockToSignal and vice-versa
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Clock.asUInt and Bool.asClock now suffice.
2016-09-21 16:17:14 -07:00
2961d92244
[testharness] vsim makefrag cleanup
2016-09-19 15:14:45 -07:00
ddcf1b4099
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 13:23:17 -07:00
63f13ae7ce
Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
2016-09-16 17:10:52 -07:00
a031686763
util: Do BlackBox Async Set/Reset Registers more properly ( #305 )
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* util: Do Set/Reset Async Registers more properly
The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.
This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).
* Tabs, not spaces, in Makefiles
* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
9e2b0aad65
Revert "allow MODEL to be something other than TestHarness"
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This reverts commit bf253aaa97
2016-09-15 11:53:05 -07:00
bf253aaa97
allow MODEL to be something other than TestHarness
2016-09-14 20:51:56 -07:00
8550582f84
remove redundant verilator rule
2016-09-14 20:31:17 -07:00
a304695ffd
Add firrtl and verilog Makefile targets to vsim
2016-09-14 20:29:59 -07:00
1308680f75
Add some async/clock utilities
2016-09-14 16:30:59 -07:00
2572cd3f7c
Add missing dependency
2016-09-14 11:50:28 -07:00
fda4c2bd76
Add a way to create Async Reset Registers and a way to easily access them with TL2
2016-09-08 20:02:07 -07:00
6be569be9f
Turn on the inferRW Firrtl pass
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Without this, all of the memories wind up as two-ported.
2016-09-07 15:27:26 -07:00
92718e4b61
fix null statement in vsli_mem_gen ala firrtl#264 ( #252 )
2016-09-07 11:04:36 -07:00
e95fe646a3
mem_gen failure doesn't create the target
2016-09-06 16:29:29 -07:00
48098f5e2d
Bump FIRRTL to instantiate Sequential Memory Macros
2016-09-06 14:48:28 -07:00
1fec9807f6
allow override of vlsi_mem_gen script
2016-09-06 14:44:12 -07:00
4a7972be31
connect testharness components via member functions ( #236 )
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to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
08089f695d
allow configuration to be in separate project from test harness
2016-09-01 10:28:07 -07:00
a19bd6de96
Get in line with FIRRTL randomization flag changes ( #231 )
2016-08-29 12:29:01 -07:00
93c801f598
Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. ( #227 )
2016-08-25 17:26:28 -07:00
4f388add67
More accurate conditional include of generated .d make fragment ( #222 )
2016-08-25 14:42:04 -07:00
96e2cefb34
Merge branch 'master' into HEAD
2016-08-22 11:37:30 -07:00
