riscv/rocket-chip
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Bump Chisel and FIRRTL for annotations refactor (#1261)

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Also brings in an autoclonetype enhancement and some bug fixes
This commit is contained in:
Jack Koenig 2018-03-07 13:22:38 -05:00 committed by Henry Cook
parent d0b46c5b8f
commit 64b707cbb6
7 changed files with 9 additions and 17 deletions
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2
chisel3

@ -1 +1 @@
Subproject commit 97871178cb511063965f971b768f91c289c4776f
Subproject commit 531dd6cb7a91b9bb642368d792e9c5e0c1c72089

2
emulator/Makefrag-verilator
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@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
%.v %.conf: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno.json
$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
cd $(generated_dir) && \

2
firrtl

@ -1 +1 @@
Subproject commit b90fc784a1819c1d7905910130a7da022214bc22
Subproject commit 6ebd1585e891d0d31cd99ef3e63038b0675cf8f9

2
src/main/scala/devices/debug/Debug.scala
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@ -938,7 +938,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
//------------------------
// DMI Register Control and Status
abstractCommandBusy := (ctrlStateReg != CtrlState(Waiting))
abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting))
ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting))

7
src/main/scala/util/GeneratorUtils.scala
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@ -10,8 +10,7 @@ import freechips.rocketchip.system.{TestGeneration, DefaultTestSuites}
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy.LazyModule
import java.io.{File, FileWriter}
import net.jcazevedo.moultingyaml._
import firrtl.annotations.AnnotationYamlProtocol._
import firrtl.annotations.JsonProtocol
/** Representation of the information this Generator needs to collect from external sources. */
case class ParsedInputNames(
@ -99,9 +98,9 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
}
def generateAnno {
val annotationFile = new File(td, s"$longName.anno")
val annotationFile = new File(td, s"$longName.anno.json")
val af = new FileWriter(annotationFile)
af.write(circuit.annotations.toArray.toYaml.prettyPrint)
af.write(JsonProtocol.serialize(circuit.annotations.map(_.toFirrtl)))
af.close()
}

9
src/main/scala/util/Misc.scala
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@ -4,7 +4,7 @@
package freechips.rocketchip.util
import Chisel._
import chisel3.experimental.{ChiselAnnotation, RawModule}
import chisel3.experimental.{dontTouch, RawModule}
import freechips.rocketchip.config.Parameters
import scala.math._
@ -14,13 +14,6 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait DontTouch {
self: RawModule =>
def dontTouch(data: Data): Unit = data match {
case agg: Aggregate =>
agg.getElements.foreach(dontTouch)
case elt: Element =>
annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!"))
}
/** Marks every port as don't touch
*
* @note This method can only be called after the Module has been fully constructed

2
vsim/Makefrag-verilog
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@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno
$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno.json
$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
cd $(generated_dir) && \