Use PROJECT rather than MODEL in name of binary and generated src files.
This commit is contained in:
Henry Cook
parent
7b8aa6c839
commit
ddcf1b4099
8
Makefrag
8
Makefrag
@ -6,6 +6,10 @@ endif
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MODEL ?= TestHarness
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PROJECT ?= rocketchip
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CFG_PROJECT ?= $(PROJECT)
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CONFIG ?= DefaultConfig
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# TODO: For now must match rocketchip.Generator
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long_name = $(PROJECT).$(CONFIG)
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CXX ?= g++
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CXXFLAGS := -O1
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@ -50,7 +54,7 @@ bootrom_img = $(base_dir)/bootrom/bootrom.img
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#---------------------------------------------------------------------
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# sed uses -E (instead of -r) for BSD support
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params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm
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params_file = $(generated_dir)/$(long_name).prm
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consts_header = $(generated_dir)/consts.$(CONFIG).h
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$(consts_header): $(params_file)
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echo "#ifndef __CONST_H__" > $@
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@ -58,7 +62,7 @@ $(consts_header): $(params_file)
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sed -E 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
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echo "#endif // __CONST_H__" >> $@
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params_file_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).prm
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params_file_debug = $(generated_dir_debug)/$(long_name).prm
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consts_header_debug = $(generated_dir_debug)/consts.$(CONFIG).h
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$(consts_header_debug): $(params_file_debug)
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echo "#ifndef __CONST_H__" > $@
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@ -6,9 +6,6 @@ generated_dir_debug = $(abspath ./generated-src-debug)
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sim_dir = .
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output_dir = $(sim_dir)/output
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BACKEND = c
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CONFIG ?= DefaultConfig
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include $(base_dir)/Makefrag
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CXXSRCS := emulator SimDTM
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@ -36,7 +33,7 @@ test:
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#--------------------------------------------------------------------
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ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
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-include $(generated_dir)/$(MODEL).$(CONFIG).d
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-include $(generated_dir)/$(long_name).d
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endif
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$(output_dir)/%.run: $(output_dir)/% $(emu)
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@ -1,19 +1,18 @@
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#--------------------------------------------------------------------
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# Verilator Generation
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#--------------------------------------------------------------------
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firrtl = $(generated_dir)/$(MODEL).$(CONFIG).fir
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firrtl_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
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verilog = $(generated_dir)/$(MODEL).$(CONFIG).v
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verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
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firrtl = $(generated_dir)/$(long_name).fir
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firrtl_debug = $(generated_dir_debug)/$(long_name).fir
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verilog = $(generated_dir)/$(long_name).v
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verilog_debug = $(generated_dir_debug)/$(long_name).v
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.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
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$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
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$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
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$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug)/%.d: $(chisel_srcs) $(bootrom_img)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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@ -58,19 +57,19 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
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cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
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headers = $(wildcard $(base_dir)/csrc/*.h)
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model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
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model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG)/V$(MODEL).h
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model_header = $(generated_dir)/$(long_name)/V$(MODEL).h
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model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
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$(emu): $(verilog) $(cppfiles) $(headers) $(consts_header) $(INSTALLED_VERILATOR)
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mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
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mkdir -p $(generated_dir)/$(long_name)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
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$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
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$(MAKE) -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
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$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
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mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \
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$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
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mkdir -p $(generated_dir_debug)/$(long_name)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)"
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$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
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$(MAKE) -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk
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@ -77,7 +77,7 @@ trait Generator extends App with HasGeneratorUtilities {
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lazy val world = config.toInstance
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lazy val params = Parameters.root(world)
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lazy val circuit = elaborate(names, params)
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lazy val longName = names.topModuleClass + "." + names.configs
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lazy val longName = names.topProject + "." + names.configs
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def writeOutputFiles() {
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TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
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@ -17,13 +17,12 @@ sim_dir = .
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output_dir = $(sim_dir)/output
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BACKEND ?= v
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CONFIG ?= DefaultConfig
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TB ?= TestDriver
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include $(base_dir)/Makefrag
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include $(sim_dir)/Makefrag
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ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
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-include $(generated_dir)/$(MODEL).$(CONFIG).d
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-include $(generated_dir)/$(long_name).d
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endif
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include $(base_dir)/vsim/Makefrag-verilog
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@ -3,27 +3,27 @@
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#--------------------------------------------------------------------
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# If I don't mark these as .SECONDARY then make will delete these internal
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# files.
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.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
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.SECONDARY: $(generated_dir)/$(long_name).fir
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firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
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firrtl: $(generated_dir)/$(long_name).fir
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.PHONY: firrtl
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$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
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$(generated_dir)/%.fir $(generated_dir)/%.d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"
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cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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$(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR)
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$(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf
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$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
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$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
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$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
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cd $(generated_dir) && \
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rm -f $@ && \
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$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@.tmp && \
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$(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
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mv $@.tmp $@
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$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
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$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(long_name).prm
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echo "\`ifndef CONST_VH" > $@
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echo "\`define CONST_VH" >> $@
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sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
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