riscv/rocket-chip
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replace verilog clock divider with one written in Chisel

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Howard Mao committed 2016-09-22 11:32:29 -07:00
1 parent cbd702e48e
commit cd96a66ba6
5 files changed
+43 -39
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vsim/Makefrag
-1
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@@ -9,7 +9,6 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
$(base_dir)/vsrc/AsyncMailbox.v \
$(base_dir)/vsrc/AsyncResetReg.v \
$(base_dir)/vsrc/AsyncSetReg.v \
$(base_dir)/vsrc/ClockDivider.v \
sim_vsrcs = \